2. 技术支持
  3. AR# 4409: SYNPLIFY: How to disable RAM inference using the syn_ramstyle attribute?
  4. AR# 44095: MIG Spartan-6 FPGA DDR2/DDR3 - MIG Output

AR# 44095

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MIG Spartan-6 FPGA DDR2/DDR3 - MIG Output

描述

This section of the MIG Design Assistant focuses on the MIG generated output for Spartan-6 FPGA DDR3/DDR2 designs. The MIG output includes RTL files for the MIG core, an example traffic generator, simulation testbench with the appropriate memory model instantiated, simulation and implementation script files, and a User Constraints Files (.ucf).These files allow users to quickly simulate the design to view functional behavior and create a bit file to run the design in hardware. Select from the options below to find information related to your specific question.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

解决方案

(Xilinx Answer 44096)- Description of MIG Spartan-6 FPGA DDR3/DDR2 design output directory structure and files.
(Xilinx Answer 44098)- Usage of MIG Virtex-6 FPGA DDR3/DDR2 Example Design
(Xilinx Answer 44320)- Usage of MIG Virtex-6 FPGA DDR3/DDR2 User Design

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
44320 MIG Spartan-6 FPGA DDR2/DDR3 - User Design Usage N/A N/A
44098 MIG Spartan-6 FPGA DDR2/DDR3 - Example Design Usage N/A N/A
44096 MIG Spartan-6 FPGA DDR2/DDR3 - Output Directory/File Descriptions N/A N/A
37499 MIG Design Assistant - Spartan-6 FPGA Core Generation N/A N/A
AR# 44095
日期 12/15/2012
状态 Active
Type 综合文章
器件
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