2. 技术支持
  3. AR# 4679: A1.5/F1.5 Virtex Map reports that an output is not connected, but does not trim the logic: Warning:xvkdr - blockcheck
  4. AR# 46790: Spartan-6 FPGA Design Assistant - Troubleshooting Common Clocking Problems

AR# 46790

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Spartan-6 FPGA Design Assistant - Troubleshooting Common Clocking Problems

描述

The Answer Record helps guide you to solutions to common problems with Clocking inSpartan-6FPGA designs.

NOTE:This Answer Record is part of the XilinxSpartan-6FPGA Solution Center(Xilinx Answer 44744).The XilinxSpartan-6FPGASolution Center is available to address all questions related toSpartan-6devices.Whether you are starting a new design withSpartan-6FPGA or troubleshooting a problem, use theSpartan-6FPGA Solution Center to guide you to the right information.

解决方案

See the information regarding theSpartan-6PLL or DCM in theClocking Debug GuideforSpartan-6DCM or PLL troubleshooting:

http://www.xilinx.com/support/troubleshoot/clocking_debug.htm

Select from the following list of common fabric related problems. Each Answer Record helps guide you to a solution.

  • (Xilinx Answer 44193)Design Advisory for Spartan-6 FPGA Speed File - Updates for DCM Phase Alignment
  • (Xilinx Answer 44706) Spartan-6 - PLL - Clock phase in the INTERNAL Mode
  • (Xilinx Answer 39627) Spartan-6 Clocking Wizard - How to get access to the PLL Dynamic Reconfiguration Port (DRP)
  • (Xilinx Answer 33019) Spartan-6 Clocking - DCM_CLKGEN Spread Spectrum Clock Generation feature support
  • (Xilinx Answer 34057) Spartan-6 LXT - GTP - The reference clock output port should directly drive BUFIO2
  • (Xilinx Answer 46141) Design Advisory for Spartan-6 - PLL CLKOUT3 Incorrect Phase Shift
  • (Xilinx Answer 34486) Spartan-6 Clocking Wizard - DCM allowed input frequency incorrect
  • (Xilinx Answer 36139) Spartan-6 - When using the DCM with Dynamic Phase Shift, how long does it take PSDONE to assert?
  • (Xilinx Answer 37648) Spartan-6, DCM_CLKGEN - After changing the M and D via SPI, how long before the LOCK re-asserts?
  • (Xilinx Answer 39184) Spartan-6 - Is it possible to drive PLLs in the top and bottom of the device using an IBUFGDS or IBUFG?
  • (Xilinx Answer 44714) PLL/MMCM DRP - Simulating XAPP878/XAPP879 Produces "Warning: Address DADDR=25"
  • (Xilinx Answer 44517) Clocking Wizard - Release Notes and Known Issues for the Clocking Wizard v3.3
  • (Xilinx Answer 21755) Spartan-6 and Spartan-3 Generation FPGA DCM - How do I handle a frequency change at the input clock of my DCM?
  • (Xilinx Answer 34937) Clocking Wizard - When the output CLK is the same as the input, the Requested and Actual can be slightly different
  • (Xilinx Answer 35781) How to do simulation on DCM/PLL/MMCM with external feedback?
  • (Xilinx Answer 37806) Spartan, Virtex, 7 Series DCM/PLL/MMCM - Can the input frequency be changed without changing the CLKIN_PERIOD attribute?

If you still have a problem after running through the suggestions, open a WebCase with Xilinx Technical Support:

http://www.xilinx.com/support/clearexpress/websupport.htm

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
44744 Spartan-6 FPGA Solution Center N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
46789 Spartan-6 FPGA Design Assistant - Troubleshooting N/A N/A
35781 How to do simulation on DCM/PLL/MMCM with external feedback? N/A N/A
44714 PLL/MMCM DRP - Simulating XAPP878/XAPP879 Produces "Warning: Address DADDR=25" N/A N/A
39184 Spartan-6 - Is it possible to drive PLLs in the top and bottom of the device using an IBUFGDS or IBUFG? N/A N/A
37648 Spartan-6, DCM_CLKGEN - After changing the M and D via SPI, how long before the LOCK re-asserts? N/A N/A
36193 ChipScope & Vivado Logic Debug - How can I trigger two ILA cores at the same time? N/A N/A
34486 Spartan-6 Clocking Wizard - DCM allowed input frequency incorrect N/A N/A
46141 有关 Spartan-6 的设计咨询 - PLL CLKOUT3 错误移相 N/A N/A
34057 Spartan6 LXT - GTP - The reference clock output port should directly drive BUFIO2 N/A N/A
33019 Spartan-6 Clocking - DCM_CLKGEN Spread Spectrum Clock Generation Feature Support N/A N/A
39627 Spartan-6 时钟向导 - 如何访问 PLL 动态重配置端口 (DRP) N/A N/A
44706 Spartan-6 PLL - Clock phase in the INTERNAL Mode N/A N/A
44517 Clocking Wizard - Release Notes and Known Issues for the Clocking Wizard v3.3 N/A N/A
37806 Spartan, Virtex, 7 Series DCM/PLL/MMCM - Can the input frequency be changed without changing the CLKIN_PERIOD attribute? N/A N/A
34937 Clocking Wizard - When the output CLK is the same as the input, the Requested and Actual can be slightly different N/A N/A
21755 Spartan-6 and Spartan-3 Generation FPGA DCM - How do I handle a frequency change at the input clock of my DCM? N/A N/A
AR# 46790
日期 02/14/2013
状态 Active
Type 综合文章
器件
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