Version Found: v1.7
Version Resolved and other Known Issues: See (Xilinx Answer 40469)
If simulating the 7 series Integrated Block for PCI Express v1.7 in Cadence IES, the tool results in the following warning message:
ncelab: *W,CSINFI (/user/nak/work/pcie_7x_v1_4_x4/pcigen1_x4/pcigen1_x4/pcigen1_x4.srcs/sources_1/ip/pcie_7x_v1_7_0/
pcie_7x_v1_7_0/example_design/xilinx_pcie_2_1_ep_7x.v,531|63): implicit wire has no fanin (board.EP.init_pattern_bus).
ncelab: *W,CSINFI: implicit wire has no fanin ({*Name Protected*}).
ncelab: *W,CSINFI: implicit wire has no fanin ({*Name Protected*}).
ncelab: *W,CSINFI: implicit wire has no fanin ({*Name Protected*}).
It is safe to ignore these waring messages. It will be fixed in the next release of the core.
NOTE: "Version Found" refers to the version where the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
Revision History
11/20/2012 - Initial release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 40469 | 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7 | N/A | N/A |
| AR# 52968 | |
|---|---|
| 日期 | 08/26/2013 |
| 状态 | Active |
| Type | 综合文章 |
| 器件 | |
| Tools | |
| IP | |