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  3. AR# 4046: Foundation Schematic Editor: Does Schematic Editor have multiple Undo capability?
  4. AR# 40469: 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7

AR# 40469

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7 Series Integrated Block for PCI Express - Release Notes and Known Issues for All Versions up to Vivado 2012.4 and ISE 14.7

描述

This Release Notes and Known Issues Answer Record is for the 7 series Integrated Block for PCI Express, first released in ISE Design Suite 13.1 and contains the following information:

  • General Information
  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator tool known issues, and design tools requirements, see the IP Release Notes Guide.

Additional documentation for this core can be found at:

https://www.xilinx.com/support/documentation/ipbusinterfacei-o_pci-express.htm

解决方案

General Information

  • The ISE 14.7 design tool release contains the v1.11 core.
  • For 7 Series Integrated Block for PCI Express v2.2 core release notes, see (Xilinx Answer 54643).
  • For 7 Series FPGAs GTX/GTH transceivers known issues and answer record list, see (Xilinx Answer 37179).

New Features

  • ISE 14.7 design tool support.

Supported Devices

  • Virtex-7, Kintex-7, Artix-7, Zynq-7000
  • 7 Series Integrated Block does not support targeting SSIT devices with the ISE tool flow. Customers that want to target SSIT devices (1500T and 2000T) must use the Vivado development environment.
  • For specific device support within each family, see the product guide.

Note: For the previous versions "New Features" and "Supported Devices", see the readme.txt or version information file available with the generated core.

Design Advisory

(Xilinx Answer 53740) - Design Advisory for 7 Series Xilinx PCI Express Cores - No Clock Output on TXOUTCLK at Cold Temperature

Known Issues

This table correlates the core version to the first ISE design tools release version in which it was included.

Core
Version
Vivado Tools
Version
ISE Tools
Version
1.11N/A14.7
1.10N/A14.6
1.9N/A14.5
1.8.12012.4.114.4.1
1.82012.414.4
1.72012.314.3
1.62012.214.2
1.5
2012.1
14.1
1.4
2012.1
14.1
1.3
N/A
13.4
1.2
N/A
13.3
1.1
N/A
13.1


Note: For 7 series FPGA Errata, see: https://www.xilinx.com/support/documentation/7_series_errata.htm.

The following table provides known issues for the 7 series Integrated Block for PCI Express.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record
Title
Version Found
Version Resolved
(Xilinx Answer 57764)TX de-emphasis setting is not set correctly on Lane 1 through Lane 7 in VHDL version of the core 1.10Not Resolved Yet
(Xilinx Answer 55529)CDC (Clock Domain Crossing) Issue1.91.10
(Xilinx Answer 55909)Designs for Artix-7 devices may not meet timing if implemented on ISE 1.9Use v2.0 in Vivado
(Xilinx Answer 55899)The core does not link train when selecting 125mhz as reference clock frequency1.9v2.1
(Xilinx Answer 55537)How do you generate the core for production Zynq devices? 1.9v2.1
(Xilinx Answer 55508)Provided NCSIM simulation script with the example design does not work1.91.10
(Xilinx Answer 55311)Downstream Memory Write transactions fail in VHDL example design simulation for the core generated with 128 bit interface width 1.9v2.1
(Xilinx Answer 54232)(ISE 14.4/ Vivado 2012.4) - How to generate the core for Artix-7 Production Silicon1.81.8.1
(Xilinx Answer 53740)(ISE 14.4 / Vivado 2012.4) - No Clock Output on TXOUTCLK at Cold Temperature 1.81.9
(Xilinx Answer 53250)(Vivado 2012.4) - Setup timing violation on userclk1 1.8Not Resolved Yet
(Xilinx Answer 53251)(ISE 14.4) - Setup timing violations on paths between ../pcie_block_i (CPU) and [../bram36_dp_bl.bram36_tdp_bl (RAM)]/ ] / [../sdp_bl.ramb36_dp_bl.ram36_bl (RAM)] 1.82.2
(Xilinx Answer 53550)
128-bit user interface with 64-bit BAR simulation is not working - malformed packet sent by the Root Port Simulation Model (DSPORT)
1.72.1
(Xilinx Answer 53056)(ISE 14.3) ERROR:Xst:2927 - Source file ../source/PCIe_portion_pipe_clock_tandem.vhd" does not exist 1.7Not Resolved Yet
(Xilinx Answer 52968)(Vivado 2012.3) Simulation warning in Cadence IES "ncelab: *W,CSINFI: implicit wire has no fanin ({*Name Protected*})" 1.71.8
(Xilinx Answer 52447) (Vivado 2012.3) userclk2 incorrectly constrained in XDC file when generating x8Gen2 core for KC705 board1.71.8
(Xilinx Answer 50683)(ISE 14.3/Vivado 2012.3) MSI Per Vector Masking Capability Support1.7Not Resolved Yet
(Xilinx Answer 51448)7 Series FPGA GTP Transceivers - RX Termination Use Modes1.6Not Resolved Yet
(Xilinx Answer 51135)The core does not link up on Z77(Ivy Bridge) platform 1.61.9/2.0
(Xilinx Answer 51381)UCF in the example design has a TIG constraint for 125 MHz clock even for Gen1 mode1.41.7
(Xilinx Answer 51285)(Vivado 2012.2) - Does not link train with XCV72000T devices1.61.7
(Xilinx Answer 50692)(ISE 14.1/Vivado 2012.1) - The core may truncate some DLLPs/TLPs during the process of going into Recovery 1.4Not Resolved Yet
(Xilinx Answer 50835)(ISE 14.2/Vivado 2012.2) - VHDL simulation support for Root Port Configuration1.6Not Resolved Yet
(Xilinx Answer 50186)
(Vivado 2012.1) - x8 Link Width not supported on Artix devices
1.5
1.6
(Xilinx Answer 47969)
(ISE 14.1) - Core generation for XC7V1500T and XC7V2000T devices
1.4
1.6
(Xilinx Answer 47907)
(Vivado 2012.1) - VHDL Root Port Configuration Support
1.4
1.6
(Xilinx Answer 47626)
(ISE 14.1/Vivado 2012.1) -VHDL Simulation Support in Endpoint Configuration
1.4
2.2
(Xilinx Answer 47627)
(ISE 14.1) - Incorrect Completion Packets Generation for Interface Width 128-bit with Configuration Other than x8Gen2
1.4
1.5
(Xilinx Answer 47628)
(ISE 14.1 / Vivado 2012.1) - Timing Violations in Certain IP Configurations
1.4
Not Resolved Yet
(Xilinx Answer 47629)
(Vivado 2012.1) - Core Configurations Other than x1Gen1 (64-bit) and x1Gen2 (64-bit) not Supported
1.4
1.5
(Xilinx Answer 47630)
(Vivado 2012.1) - VHDL Support in Endpoint Configuration
1.4
1.5
(Xilinx Answer 47632)
(Vivado 2012.1) - Root Port Configuration Support
1.4
1.5
(Xilinx Answer 47316)
Enabling OOB Clock Mode
1.3
1.6
(Xilinx Answer 44732)
ISIM example script fails to compile when using VHDL
1.2
1.6
(Xilinx Answer 44682)
VHDL Flow Does Not Produce VHDL for MGT Wrapper Files
1.2
Not Resolved Yet
(Xilinx Answer 44681)Is Synplify supported?
1.1
Verilog Support in v1.6
(Xilinx Answer 44643)
Signals cfg_pm_halt_l1, cfg_pm_force_state[1:0] seem to imply APSM L1 is supported
1.2
1.3
(Xilinx Answer 44625)
VHDL Simulation Results in "Failure: Rx Simulation Timeout"
1.2
1.3
(Xilinx Answer 44351)
Blocks on left side may have unpredictable behavior when using ISE 13.2
1.1
1.2
(Xilinx Answer 42873)
Selectable Devices That Are Not Supported.
1.1
1.2
(Xilinx Answer 42830)
sys_reset_n does not have a pin location constraint.
1.1
1.2
(Xilinx Answer 43107)
Missing BRAM LOC constraints in UCF.
1.1
1.2
(Xilinx Answer 45541)
Pin to Pin Skew timing constraint failure targeting -2L
1.1
1.3
(Xilinx Answer 40595)
x8 Gen 1 and x4 Gen 2 designs using 128-bit interface do not simulate
1.1
1.1 Rev 1
(Xilinx Answer 41053)
Simulation link up takes too long
1.1
1.1 Rev 1
(Xilinx Answer 41271)
RECRC Check and Trim TLP Digest overlap.
1.1
1.1 Rev 1
(Xilinx Answer 45734)
MSI-X Table Size Field in Customization GUI Should Be Entered as Decimal Number
1.1
1.1 Rev 1
(Xilinx Answer 42838)
A Version 1.1 Core Does Not Implement in ISE Design Suite 13.2 Due to Port Changes on GTXE2_COMMON
1.1
1.1 Rev 1


Other Information

(Xilinx Answer 47341)7 series Integrated Block Wrapper for PCI Express v1.3m_axis_rx_tlast never assert on 128-bit interface GEN2 x8 core
(Xilinx Answer 51402)7 Series Integrated Block for PCI Express v1.6Incorrect RX_CM_TRIM setting for Artix-7 FPGAs
(Xilinx Answer 52400)7 Series Integrated Block for PCI Express v1.9/2.0Asynchronous Clocking Support
(Xilinx Answer 52487)7 Series Integrated Block Wrapper for PCI Express v1.7 (ISE 14.3/Vivado 2012.3)Example Design Reset and Clock Buffer Location for AC701 board
(Xilinx Answer 55357)7 Series Integrated Block for PCI Express v1.8How do you allow messages and legacy interrupts to be routed to the root port?


Revision History

02/03/2014Minor update
10/23/2013Updated for ISE 14.7 Release
10/08/2013Added (Xilinx Answer 57764)
06/19/2013Updated for ISE 14.6 Release
06/13/2013Added (Xilinx Answer 55529)
05/24/2013Added (Xilinx Answer 55909)
05/18/2013Added (Xilinx Answer 55899)
05/02/2013Added (Xilinx Answer 55537)
04/12/2013Added (Xilinx Answer 55508)
04/03/2013Updated for ISE 14.5 Release
02/14/2013Added (Xilinx Answer 54232)
01/21/2013Added (Xilinx Answer 53740)
12/18/2012Updated for ISE 14.4/Vivado 2012.4 Release
11/26/2012Added (Xilinx Answer 53056)
11/20/2012Added (Xilinx Answer 52968)
10/03/2012Updated for ISE 14.3/Vivado 2012.3 Release
09/25/2012Added (Xilinx Answer 51448)
09/17/2012Added (Xilinx Answer 51135)
09/06/2012Added (Xilinx Answer 51381)
08/15/2012Added (Xilinx Answer 51285)
07/25/2012Updated for v1.6
05/31/2012- Added (Xilinx Answer 50186)
05/18/2012Added (Xilinx Answer 47969)
05/08/2012Updated for ISE 14.1 and Vivado 2012.1 design tools and v1.4
05/01/2012Added (Xilinx Answer 47316)
03/06/2012Updated title for (Xilinx Answer 44681)
01/18/2012Updated for ISE 13.4 Design Suite and v1.3.
10/21/2011Updated for ISE 13.3 Design Suite and v1.2
10/06/2011Added (Xilinx Answer 44353) and (Xilinx Answer 44351)
09/26/2011Added (Xilinx Answer 43347) and (Xilinx Answer 43423)
09/07/2011Added (Xilinx Answer 43949)
08/12/2011Changed known issues to table format
07/14/2011Added (Xilinx Answer 43107)
07/06/2011Updated for ISE 13.2 Design Suite and v1.1 Rev 1
03/29/2011Added (Xilinx Answer 41509)
03/28/2011Added (Xilinx Answer 41271)
03/03/2011Added (Xilinx Answer 41053)
03/01/2011Initial release

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
51901 Virtex-7 FPGA VC709 连接套件 — 已知问题与版本说明的主要答复记录 N/A N/A
45382 Virtex-7 FPGA VC707 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
45934 Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
51900 Artix-7 FPGA AC701 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
51233 Virtex-7 FPGA VC707 Evaluation Kit - Board Debug Checklist N/A N/A
50079 Kintex-7 FPGA KC705 Evaluation Kit - Board Debug Checklist N/A N/A
54139 Artix-7 FPGA AC701 Evaluation Kit - Board Debug Checklist N/A N/A
54355 Virtex-7 FPGA VC709 Connectivity Kit - Board Debug Checklist N/A N/A

子答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
47316 7 Series Integrated Block for PCI Express v1.3 - Enabling OOB Clock Mode N/A N/A
45734 7 Series Integrated Block for PCI Express - MSI-X Table Size field in customization GUI should be entered as decimal number N/A N/A
45541 7 Series Integrated Block for PCI Express - Pin to Pin Skew timing constraint failure when targeting -2L speed grade N/A N/A
44682 7 系列 PCI Express (PCIe) 集成模块- VHDL 方式不产生MGT的VHDL封装文件 N/A N/A
44681 用于PCI Express 的7系列集成模块-支持Synplify综合吗？ N/A N/A
44643 7 Series Integrated Block for PCI Express - Signals cfg_pm_halt_l1, cfg_pm_force_state[1:0] seem to imply APSM L1 is supported N/A N/A
44625 7 Series Integrated Block for PCI Express - VHDL simulation results in "Failure: Rx Simulation Timeout" N/A N/A
43107 7 Series Integrated Block Wrapper for PCI Express - Missing block RAM LOC constraints in UCF N/A N/A
42838 7 Series Integrated Block for PCI Express - A Version 1.1 Core Does Not Implement in ISE Design Suite 13.2 Due to Port Changes on GTXE2_COMMON N/A N/A
42164 7 Series Integrated Block Wrapper v1.1 for PCI Express - Component Switching Limit Error Occurs with x8 gen2 Core when a Virtex-7 -1 Speed Grade Is Targeted N/A N/A
41271 7 Series Integrated Block for PCI Express - RECRC Check and Trim TLP Digest overlap N/A N/A
41053 7 Series Integrated Block for PCI Express - Simulation link up takes too long N/A N/A
40595 7 Series Integrated Block for PCI Express - x8 Gen 1 and x4 Gen 2 designs using 128-bit interface do not simulate N/A N/A
42873 7 Series Integrated Block for PCI Express - Selectable Devices That Are Not Supported N/A N/A
47907 7 Series Integrated Block for PCI Express v1.5 (Vivado 2012.1) - VHDL Root Port Configuration Support N/A N/A
47862 7 Series Integrated Block for PCI Express v1.5 (ISE 14.1/Vivado 2012.1) - Download, Installation and Usage Instructions N/A N/A
47632 7 Series Integrated Block for PCI Express v1.4 (Vivado 2012.1) - Root Port Configuration Support N/A N/A
47630 7 Series Integrated Block for PCI Express v1.4 (Vivado 2012.1) - VHDL Support in Endpoint Configuration N/A N/A
47629 7 Series Integrated Block for PCI Express v1.4 (Vivado 2012.1) - Core configurations other than x1Gen1 (64-bit) and x1Gen2 (64-bit) are not supported N/A N/A
47628 7 Series Integrated Block for PCI Express v1.4 (ISE 14.1 / Vivado 2012.1) - Timing violations in certain IP configurations N/A N/A
47626 7 Series Integrated Block for PCI Express v1.5 (ISE 14.1/Vivado 2012.1) - VHDL Simulation Support for Endpoint Configuration N/A N/A
47969 7 Series Integrated Block for PCI Express v1.4 (ISE 14.1) - Core generation for XC7V1500T and XC7V2000T devices N/A N/A
51285 7 Series Integrated Block Wrapper for PCI Express v1.6 (Vivado 2012.2) - Does not link train with XCV72000T devices N/A N/A
51381 用于 PCI Express v1.4 的 7 系列集成模块 - 示例设计中的 UCF 针对 125 MHz 时钟具有 TIG 约束，即使在 Gen1 模式下也如此。 N/A N/A
52447 7 Series Integrated Block for PCI Express - v1.7 userclk2 incorrectly constrained in XDC file when generating x8Gen2 core N/A N/A
52968 7 Series Integrated Block for PCI Express v1.7 (Vivado 2012.3) - Simulation warning in Cadence IES "ncelab: *W,​CSINFI: implicit wire has no fanin ({*Name Protected*})" N/A N/A
53250 7 Series Integrated Block for PCI Express - v1.8 (Vivado 2012.4) - Setup timing violation on userclk1 N/A N/A
53251 7 Series Integrated Block for PCI Express - v1.8 (ISE 14.4) - Setup timing violations on paths between ../pcie_block_i (CPU) and [../bram36_dp_bl.bram36_tdp_bl (RAM)]/ ] / [../sdp_bl.ramb36_dp_bl.ram36_bl (RAM)] N/A N/A
53550 7-series Integrated Block Wrapper for PCI Express v1.7 - 128-bit user interface with 64-bit BAR simulation is not working - malformed packet sent by the Root Port Simulation Model (DSPORT) N/A N/A
53740 有关 7 系列 Xilinx PCI Express 内核的设计咨询 - 在低温情况下，TXOUTCLK 上无时钟输出 N/A N/A
54232 面向 PCI Express v1.8 (ISE 14.4/2012.4) 的 7 系列 Integrated Block Wrapper (ISE 14.4/2012.4)——如何生成针对 Artix-7 量产芯片的内核？ N/A N/A
55508 7 系列 PCI Express (PCIe) 集成模块 v1.9 - 包含范例设计的 NCSIM 仿真脚本无效 N/A N/A
55899 PCI Expres® v1.9 的 7 系列集成模块 - 当选择125 MHz作为参考时钟频率时，核未链接行列。 N/A N/A
55909 7 Series Integrated Block for PCI Express v1.9 - Designs for Artix-7 devices might not meet timing if implemented on ISE design tools N/A N/A

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
40595 7 Series Integrated Block for PCI Express - x8 Gen 1 and x4 Gen 2 designs using 128-bit interface do not simulate N/A N/A
41271 7 Series Integrated Block for PCI Express - RECRC Check and Trim TLP Digest overlap N/A N/A
43347 Kintex-7 FPGA Initial Engineering Sample (ES) - Known Issues Master Answer Record N/A N/A
AR# 40469
日期 10/08/2019
状态 Active
Type 版本说明
IP
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