AR# 55085

描述

Version Found: Upgrading from v1.4 or earlier core to v2.0

In the Vivado 2013.1 tool, when upgrading from 7 Series Integrated Block Wrapper for PCI Express v1.8 core or earlier, errors similar to the following occur for a few of the core ports:

"ERROR: [Synth 8-448] named port connection 'PIPE_PCLK_IN' does not exist for instance 'pcie3_7x_v1_4_0_i' of module 'pcie3_7x_v1_4_0' [/.../design.srcs/sources_1/imports/pcie3_7x_v1_4_0/pcie3_7x_v1_4_0/example_design/xilinx_pcie_3_0_7vx_ep.v:412]"

"ERROR: [Synth 8-448] named port connection 'PIPE_PCLK_IN' does not exist for instance 'pcie3_7x_v1_4_0_i' of module 'pcie3_7x_v1_4_0' [/.../design.srcs/sources_1/imports/pcie3_7x_v1_4_0/pcie3_7x_v1_4_0/example_design/xilinx_pcie_3_0_7vx_ep.v:412]"

解决方案

To drive consistency between Xilinx IPs, signal names in the Verilog cores have been changed to use all lowercase. Therefore, the higher level module where the core is instantiated should now have the following signals listed below in lowercase. Please upgrade the core first before changing the core instantiation in the design.

PIPE_*
ICAP_*

There are also new signals need to be added into the core instantiation:

drp_*
init_pattern_bus
cfg_local_err

The * substitutes all character(s) following the specified prefix signal names.

In the example above, "PIPE_PCLK_IN" is now "pipe_pclk_in".

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