AR# 56376: LogiCORE DUC/DDC Compiler v3.0 - Some configurations of the DUC/DDC Compiler v3.0 core do not simulate correctly when Vivado Simulator is used to perform behavioral simulation
AR# 56376
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LogiCORE DUC/DDC Compiler v3.0 - Some configurations of the DUC/DDC Compiler v3.0 core do not simulate correctly when Vivado Simulator is used to perform behavioral simulation
描述
Some configurations of the DUC/DDC Compiler v3.0 core do not simulate correctly when Vivado Simulator is used to perform behavioral simulation. The output of the core, SREG_PRDATA, will be all-X.
解决方案
This is a known issue with DUC/DDC Compiler v3.0.
A workaround is to use Mentor Graphics ModelSim or QuestaSim as the simulator for behavioral simulation. This may be configured in the Vivado GUI project options dialog.
For a detailed list of LogiCORE IP DUC/DDC Compiler Release Notes and Known Issues, see (Xilinx Answer 54476).