AR# 56893

描述

This answer record provides videos related to Xilinx PCI Express solutions.

This article is part of the PCI Express Solution Centre

解决方案

DMa for PCI Express

https://www.youtube.com/watch?v=TzzzM97L4HI

Xilinx UltraScale+ PCIe Gen3 x16 hardened IP passes PCI SIG compliance test: See it now on video running at 100Gbps+

https://forums.xilinx.com/t5/Xcell-Daily-Blog/Xilinx-UltraScale-PCIe-Gen3-x16-hardened-IP-passes-PCI-SIG/ba-p/694911

AXI PCIe with MIG on a KCU105 using WinDriver from Jungo Connectivity

http://www.xilinx.com/video/fpga/ultrascale-designs-fast-ipi-ddr4-pcie-windriver.html

UltraScale PCIe PIPE Simulation with Mentor QVIP

https://www.youtube.com/watch?v=VWnkg01rJEY

How to create a PCI Express Design in an UltraScale FPGA:

https://www.youtube.com/watch?v=1YgviyNfLYY

UltraScale PCI Express - The Power of 4:

https://www.youtube.com/watch?v=G8n86wvh2ig

AXI PCI Express MIG Subsystem Built in IPI:

https://www.youtube.com/watch?v=0KnvW_6Bgu0

Zynq PCI Express Root Complex Made Simple:

https://www.youtube.com/watch?v=D1vOFBSuWAc

Virtex-7 PCI Express Gen3 Demo:

https://www.youtube.com/watch?v=IOHgltR11QY

Xilinx Virtex-6 FPGA PCI Express Demo:

http://www.youtube.com/watch?v=wxD71xdmmkE

PCIe x8 Gen3 Running on a Xilinx Kintex-7 FPGA:

https://www.youtube.com/watch?v=mAw7Ao6P6zU

Inserting Debug Cores into the Design:

https://www.youtube.com/watch?v=bU8BsPuIyOo&index=29&list=PL35626FEF3D5CB8F2

Programming and Debugging a Design in Hardware:

https://www.youtube.com/watch?v=i8axs4hw2f4&list=PL35626FEF3D5CB8F2&index=30

Debugging at Device Startup:

https://www.youtube.com/watch?v=dt3YTlWfeHw&list=PL35626FEF3D5CB8F2&index=104

Tandem Configuration of 7 Series Devices:

https://www.youtube.com/watch?v=N5OVPtSTwuA