Tool versions affected: Vivado 2014.1, 2014.2 and 2014.3
Version Resolved and other Known Issues:
See (Xilinx Answer 54645) for Virtex-7 FPGA Gen3 Integrated Block for PCI Express
See (Xilinx Answer 54646) for AXI Bridge for PCI Express
See (Xilinx Answer 54643) for 7 Series Integrated Block for PCI Express
When implementing the 7-Series/Virtex-7 FGPA Gen3 Integrated Block for PCI Express/ AXI Bridge for PCI Express core example design in Vivado 2014.1, 2014.2 and 2014.3, the check_timing tool reports a number of 'constant_clock' and 'unconstrained_internal_endpoints'.
The issue is seen only when the core is configured as Gen1.
When a design has unconstrained timing paths due to this issue, the PCIe design may not link train or it may experience intermittent training issues such as not training to the full link width specified.
Another possible issue is that designs may have higher bit error rates than normal.
Designs that have these unconstrained paths must have the constraint specified below added to the XDC file and the design must be placed and routed again to ensure proper operation across process, voltage and temperature.
This is a known issue to be fixed in Vivado 2014.4.
In the example design, there are clocks muxed by a BUFGCTRL to select the correct clocks for Gen1 and Gen2 speed.
For the correct timing analysis, BUFGCTRL input selection pins S0 and S1 should be '1' and '0' respectively.
This is realized by the following constraints in the example design XDC file.
set_case_analysis 1 [get_pins {pcie3_7x_0_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S0}]
set_case_analysis 0 [get_pins {pcie3_7x_0_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S1}]
In the *pipe_clock.v file, these is an inverter on the S0 input of BUFGCTRL.
begin : pclk_i1_bufgctrl
//---------- PCLK Mux ----------------------------------
BUFGCTRL pclk_i1
(
//---------- Input ---------------------------------
.CE0 (1'd1),
.CE1 (1'd1),
.I0 (clk_125mhz),
.I1 (clk_250mhz),
.IGNORE0 (1'd0),
.IGNORE1 (1'd0),
.S0 (~pclk_sel),
.S1 ( pclk_sel),
//---------- Output --------------------------------
.O (pclk_1)
);
end
The inverter (LUT1) is pushed into BUFGCTRL pins(S0) during the design implementation optimization phase.
This leads to a mismatch in the intended timing analysis with set_case_analysis constraints resulting in constant_clock and unconstrained_internal_endpoints.
The workaround for this issue is to prevent this optimization by doing the following:
(* dont_touch = "true" *) reg pclk_sel = 1'd0;
For Virtex-7 FPGA Gen3 Integrated Block for PCI Express Core:
set_property DONT_TOUCH true [get_cells -of [get_nets -of [get_pins {pcie3_7x_0_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S0}]]]
set_property DONT_TOUCH true [get_cells -of [get_nets -of [get_pins {pcie_7x_0_support_i/pipe_clock_i/pclk_i1_bufgctrl.pclk_i1/S0}]]]
For AXI Bridge for PCI Express:
set_property DONT_TOUCH true [get_cells axpci0_i/U0/comp_axi_enhanced_pcie/comp_enhanced_core_top_wrap/axi_pcie_enhanced_core_top_i/pcie_7x_v2_0_2_inst/pcie_top_with_gt_top.gt_ges.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_i1_bufgctrl.pclk_i1_i_1]
Note: Please make sure the hierarchy names are correct.
The hierarchy will change based on the version of the core used, where the core is instantiated in the design, and if the the shared clocking option was used when generating the PCIe core.
Revision History:
11/04/2014 - Initial Release
| AR# 62296 | |
|---|---|
| 日期 | 11/10/2014 |
| 状态 | Active |
| Type | 设计咨询 |
| Tools | |
| IP | |