This answer record contains a list of Vivado Design Suite graphical user interface and project management known issues for Vivado IDE 2015.x.
Outstanding Known Issues in Vivado Design Suite 2015.4
| (Xilinx Answer 53243) | "Replace File" directory browser does not update "Date Modified" field |
| (Xilinx Answer 55052) | Vivado does not preserve XDC wildcards in generated Design Check Point (DCP) |
| (Xilinx Answer 55418) | Message suppression rules are not editable |
| (Xilinx Answer 58937) | Simulating IP core generated files gives: ERROR: [XSIM 43-3225] Can not find design unit work.<IP core TB> in library work located at xsim.dir/work |
| (Xilinx Answer 64191) | CRITICAL WARNING: [Pfi 67-14] Hardware Handoff if original location of .hwdef file is not found |
| (Xilinx Answer 65564) | Mem file not copied to simulation directory - ERROR: [VRFC 10-451] cannot open file 'int_infile |
| (Xilinx Answer 66967) | Exporting simulation files for Questa simulator generates files for all supported simulation tools |
| (Xilinx Answer 66968) | Write_debug_probes command is not issued if opt_design is disabled |
Known Issues Resolved in Vivado 2015.4
| (Xilinx Answer 65581) | After creating a new project, the default part is used unless the user specifically clicks on the desired part to select it |
| (Xilinx Answer 65591) | Deleting the active run of a Vivado project can leave the project in an undefined state |
| (Xilinx Answer 66361) | Synthesis hang on Linux OS if project has a space in the name |
Known Issues Resolved in Vivado 2015.3
| (Xilinx Answer 64948) | Zynq-7000 FBV484 Package does not reflect correct package delay for PS7 DDR Configuration |
| (Xilinx Answer 64333) | Breakpoint setting does not work in GUI when the source file has a space in its path |
| (Xilinx Answer 60140) | Vivado runs hang if the project is created or copied to a name including parentheses |
| (Xilinx Answer 64698) | VHDL Configuration architecture does not show up correctly in the Vivado hierarchy window |
| (Xilinx Answer 65516) | Generating targets for OOC block Design in projectless flow gives [Common 17-53] User Exception: No open project |
| (Xilinx Answer 65559) | Export Hardware fails if Block Design contains locked IP cores |
| (Xilinx Answer 60242) | calibration.elf is not used in behavioral simulation for MIG UltraScale example design |
| (Xilinx Answer 64209) | Tcl script that removes and then adds a block with the same name causes a crash |
| (Xilinx Answer 64640) | When I start Vivado from a shell, I see: WARNING: [Common 17-204] Your XILINX environment variable is undefined |
| (Xilinx Answer 64708) | A module set as "Out of Context" for synthesis, is treated as a black box for behavioral simulation |
Known Issues Resolved in Vivado 2015.2
| (Xilinx Answer 64228) | 2015.1 Vivado Lab tools edition gives java.lang.NullPointerException when changing dashboard |
| (Xilinx Answer 64443) | set_operating_conditions does not change project part when Vccint value is set outside the range of the current device |
| (Xilinx Answer 64481) | Vivado exits unexpectedly when the GUI is launched through a remote access and using an Asian operating system |
| (Xilinx Answer 64643) | Open Example Project leads to exception if only Virtex UltraScale family is installed |
| (Xilinx Answer 64707) | An internal exception will occur in Vivado 2015.1 if Connection Automation is run in IPI with two instances of Vivado open |
Known Issues Resolved in Vivado 2015.1
| (Xilinx Answer 62708) | ASYNC_REG property is not showing in the Property window |
| (Xilinx Answer 62768) | Generated 3rd party simulator scripts created with the wrong library for simulation testbench files if they are assigned to a different library than the design VHDL files |
| (Xilinx Answer 62834) | LUT equation box displays incorrect value when the LUT4's INIT value is 16'hABFB |
| (Xilinx Answer 62889) | Vivado IDE Error "Abnormal program termination (11)" when OBUFDS that has a LOC constraint set but no IOSTANDARD |
| (Xilinx Answer 63180) | Selecting "Place ports in an Area" and then clicking on the Floorplanner will cause an Internal Exception |
| (Xilinx Answer 63347) | Vivado gives Abnormal program termination while opening an EDIF netlist created with newer versions of Synopsys Synplify / Pro |
| (Xilinx Answer 63662) | User Created DRC fails to be reported as proper severity |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 63538 | Vivado Design Suite 2015 - Known Issues | N/A | N/A |
| AR# 63954 | |
|---|---|
| 日期 | 04/18/2016 |
| 状态 | Active |
| Type | 已知问题 |
| Tools | |