For JESD204 designs, clocks must be stable for the IP to work correctly. In particular, the clock needs to be stable when SYSREF is being sampled, otherwise clock skew might be observed.
A good JESD204 design will hold everything in reset until clocks are stable.
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 54480 | LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools | N/A | N/A |
| 61911 | LogiCORE IP JESD204 PHY core - Release Notes and Known Issues | N/A | N/A |
| AR# 66576 | |
|---|---|
| 日期 | 02/12/2016 |
| 状态 | Active |
| Type | 综合文章 |
| IP | |