When using the 7 Series Integrated Block for PCI Express core example design in Vivado 2013.4, incorrect behavior is seen with completion being sent out when s_axis_tx_tready is not continuously asserted.
This article is part of the PCI Express Solution Centre
| (Xilinx Answer 34536) | Xilinx Solution Center for PCI Express |
This is a known issue with the example design logic. This has been fixed in Vivado 2014.2.
To work around this issue, replace the following code:
reg s_axis_tx_tready_i;
always @(posedge user_clk)
begin
if (user_reset)
s_axis_tx_tready_i <= #TCQ 1'b0;
else
s_axis_tx_tready_i <= #TCQ s_axis_tx_tready;
end
Replace it with this code:
wire s_axis_tx_tready_i;
assign s_axis_tx_tready_i = s_axis_tx_tready
| AR# 67006 | |
|---|---|
| 日期 | 04/18/2016 |
| 状态 | Active |
| Type | 综合文章 |
| IP | |