This answer record lists the known issues for the Vivado Simulator in the Vivado 2016.x releases.
Each known issue includes a link to another answer record that contains additional information on the issue.
Outstanding Issues in Vivado 2016.3
| (Xilinx Answer 67272) | Vivado Simulator 2016.1 - ERROR: [XSIM 43-3238] Failed to link the design |
| (Xilinx Answer 67870) | 2016.3 - Compile Simlib - Error in XPM library compilation when -ise_install_path option is used |
| (Xilinx Answer 67890) | 2016.3 - Vivado Simulator - Scope for pre-compiled IP instance is missing in Scope Window |
Issue resolved in Vivado 2016.3
| (Xilinx Answer 67013) | 2016.1 - compile_simlib fails with 3-4 errors for all simulators with -ise_install_path option |
| (Xilinx Answer 67015) | compile_simlib - Abnormal program termination (EXCEPTION_ACCESS_VIOLATION) |
| (Xilinx Answer 65453) | Vivado 2015.x - ERROR: [XSIM 43-3190] The "System Verilog real type port" is not supported yet for simulation |
| (Xilinx Answer 67275) | 2016.1 - Simulation - Export Simulation leads to an error when a space is in the directory path |
| (Xilinx Answer 67382) | 2016.1 Vivado Simulation - compile_simlib targeting ModelSim DE fails on Linux 64-bit OS |
| (Xilinx Answer 67235) | 2016.1 Vivado IP Flows - IP pointing to XPM macros in Vivado 2016.1 break existing Non-project scripts |
| (Xilinx Answer 67150) | 2016.1 - Simulation Libraries - Compiling Simulation Libraries also includes IP |
| (Xilinx Answer 67808) | Tactical Patch - Vivado 2016.2 - XSIM - Xilinx_AXI_BFM license is held in XSIM but checked in for third Party Simulators |
Outstanding Issues in Vivado 2016.2
| (Xilinx Answer 67013) | 2016.1 - compile_simlib fails with 3-4 errors for all simulators with -ise_install_path option |
| (Xilinx Answer 67015) | compile_simlib - Abnormal program termination (EXCEPTION_ACCESS_VIOLATION) |
| (Xilinx Answer 65453) | Vivado 2015.x - ERROR: [XSIM 43-3190] The "System Verilog real type port" is not supported yet for simulation |
| (Xilinx Answer 67275) | 2016.1 - Simulation - Export Simulation leads to an error when a space is in the directory path |
| (Xilinx Answer 67272) | Vivado Simulator 2016.1 - ERROR: [XSIM 43-3238] Failed to link the design |
| (Xilinx Answer 67382) | 2016.1 Vivado Simulation - compile_simlib targeting ModelSim DE fails on Linux 64-bit OS |
| (Xilinx Answer 67235) | 2016.1 Vivado IP Flows - IP pointing to XPM macros in Vivado 2016.1 break existing Non-project scripts |
| (Xilinx Answer 67150) | 2016.1 - Simulation Libraries - Compiling Simulation Libraries also includes IP |
| (Xilinx Answer 67808) | Tactical Patch - Vivado 2016.2 - XSIM - Xilinx_AXI_BFM license is held in XSIM but checked in for third Party Simulators |
Issue resolved in Vivado 2016.2
| (Xilinx Answer 67142) | 2016.1 - Simulation - Project Utilities Tcl App update required for Export Simulation |
| (Xilinx Answer 66993) | 2016.1 - compile_simlib - RAM64X8SW VHDL model not getting compiled by compile_simlib |
| (Xilinx Answer 67468) | 2016.1 - Simulation - XADC simulation model includes unnecessary check for 'DWE' pulse width |
Outstanding Issues in Vivado 2016.1
| (Xilinx Answer 67013) | 2016.1 - compile_simlib fails with 3-4 errors for all simulators with -ise_install_path option |
| (Xilinx Answer 67015) | compile_simlib - Abnormal program termination (EXCEPTION_ACCESS_VIOLATION) |
| (Xilinx Answer 67142) | 2016.1 - Simulation - Project Utilities Tcl App update required for Export Simulation |
| (Xilinx Answer 65453) | Vivado 2015.x - ERROR: [XSIM 43-3190] The "System Verilog real type port" is not supported yet for simulation |
| (Xilinx Answer 67275) | 2016.1 - Simulation - Export Simulation leads to an error when a space is in the directory path |
| (Xilinx Answer 67272) | Vivado Simulator 2016.1 - ERROR: [XSIM 43-3238] Failed to link the design |
| (Xilinx Answer 66993) | 2016.1 - compile_simlib - RAM64X8SW VHDL model not getting compiled by compile_simlib |
| (Xilinx Answer 67382) | 2016.1 Vivado Simulation - compile_simlib targeting ModelSim DE fails on Linux 64-bit OS |
| (Xilinx Answer 67235) | 2016.1 Vivado IP Flows - IP pointing to XPM macros in Vivado 2016.1 break existing Non-project scripts |
| (Xilinx Answer 67150) | 2016.1 - Simulation Libraries - Compiling Simulation Libraries also includes IP |
| (Xilinx Answer 67468) | 2016.1 - Simulation - XADC simulation model includes unnecessary check for 'DWE' pulse width |
Issue resolved in Vivado 2016.1
| (Xilinx Answer 66011) | Vivado 2015.3/2015.4 - export_simulation ignoring -lib_map_path option in Windows |
| (Xilinx Answer 66062) | Vivado Simulator 2015.4 - FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover |
| (Xilinx Answer 65571) | Vivado 2015.3/2015.4 - Export Simulation script with single step option fails for Cadence IUS |
| (Xilinx Answer 65564) | 2015.4 Vivado - Mem file not copied to simulation directory - ERROR: [VRFC 10-451] cannot open file 'int_infile |
| AR# 67012 | |
|---|---|
| 日期 | 10/13/2016 |
| 状态 | Active |
| Type | 已知问题 |
| Tools | |