Version Found: v3.0 (Rev3)
Version Resolved and other Known Issues: See (Xilinx Answer 54643)
When I implement a design with the 7 Series Integrated Block for PCI Express core in a Gen2x1 configuration in Vivado 2014.3, my design runs into a PCIe link issue.
The link does not train properly. The issue is seen with Gen2x1 configuration only. All other configurations work without any issue.
This article is part of the PCI Express Solution Centre
| (Xilinx Answer 34536) | Xilinx Solution Center for PCI Express |
This is a known issue and has been fixed in Vivado 2014.4.
Revision History:
04/15/2016 - Initial Release
| AR# 67039 | |
|---|---|
| 日期 | 04/21/2016 |
| 状态 | Active |
| Type | 综合文章 |
| IP | |