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  3. AR# 6902:
  4. AR# 69027: JESD204 - Single Lane JESD204 Transmit Example Design simulations timing out when using QuestaSim

AR# 69027

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JESD204 - Single Lane JESD204 Transmit Example Design simulations timing out when using QuestaSim

描述

When running a JESD204 Single Lane Transmit configuration example design using QuestaSim, a simulation time-out might occur.  

 

解决方案

This time-out scenario can be prevented by updating the Elaboration settings in Vivado Design Suite before launching the simulation.

In the Project Settings, under the Elaboration tab, add the '-noprotectopt' switch under more options.

 

g

 

This ensures that the switch is added to the elaborate.do file and the simulation will run without timing out.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
65479 JESD204B - Single Lane JESD204 Transmit Example Design Simulations Timing Out When Using QuestaSim N/A N/A
AR# 69027
日期 04/26/2017
状态 Active
Type 综合文章
IP
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