(c) Copyright 2018 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.
DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
CRITICAL APPLICATIONS Xilinx products are not designed or intended to be fail- safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
100M/1G TSN Subsystem (2.0)
* Version 2.0 (Rev. 2)
* Feature Enhancement: Endpoint Packet Switching and Endpoint Extension Features added
* Feature Enhancement: Internal Physical Interface support added
* Revision change in one or more subcores
10G Ethernet MAC (15.1)
* Version 15.1 (Rev. 6)
* No changes
10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)
* Version 6.0 (Rev. 14)
* Bug Fix: linting fixes.
* Bug Fix: Fixes for Hold time violations.
* Revision change in one or more subcores
10G Ethernet Subsystem (3.1)
* Version 3.1 (Rev. 10)
* General: Updated constraints to improve constraint processing speed
* Revision change in one or more subcores
10G/25G Ethernet Subsystem (2.5)
* Version 2.5
* Bug Fix: Updated AXI files for optimization
* Bug Fix: Updated file for AN/LT Logic and RSFEC Runtime switching configuration
* Feature Enhancement: Added support FEC and Pause for MAC+PCS/PMA 32 bit variant
* Other: added new devices support
* Revision change in one or more subcores
1G/10G/25G Switching Ethernet Subsystem (2.2)
* Version 2.2
* Bug Fix: Updated for timing DRCs
* Feature Enhancement: Added Control and Status port support
* Feature Enhancement: Added Pause support
* Feature Enhancement: Added LT / FEC support
* Feature Enhancement: SGMII support for 32-bit PCS only variant
* Other: added new devices support
* Revision change in one or more subcores
1G/2.5G Ethernet PCS/PMA or SGMII (16.1)
* Version 16.1 (Rev. 5)
* Feature Enhancement: Added 2.5G speed support for Artix-7 -2L devices
* Feature Enhancement: Added support for preamble shrinkage for 2.5G core speed
* Revision change in one or more subcores
32-bit Initiator/Target for PCI (7 Series) (5.0)
* Version 5.0 (Rev. 12)
* Added constraints for xc7a15t for 66MHz
3GPP LTE Channel Estimator (2.0)
* Version 2.0 (Rev. 15)
* No changes
3GPP LTE MIMO Decoder (3.0)
* Version 3.0 (Rev. 14)
* No changes
3GPP LTE MIMO Encoder (4.0)
* Version 4.0 (Rev. 13)
* No changes
3GPP Mixed Mode Turbo Decoder (2.0)
* Version 2.0 (Rev. 17)
* No changes
3GPP Turbo Encoder (5.0)
* Version 5.0 (Rev. 14)
* General: Support for new devices. No change in functionality
* Revision change in one or more subcores
3GPPLTE Turbo Encoder (4.0)
* Version 4.0 (Rev. 14)
* No changes
40G/50G Ethernet Subsystem (2.4)
* Version 2.4
* Bug Fix: Updated example design files for TX_unfout
* Bug Fix: Updated files for ANLT+ RSFEC validation failures
* Feature Enhancement: Added watchdog timer in core to reset RX GT
* Feature Enhancement: Added LAUI with Transcode and LAU2 support
* Feature Enhancement: Added GTM support with KP4FEC
* Other: added new devices support
* Revision change in one or more subcores
64-bit Initiator/Target for PCI (7 Series) (5.0)
* Version 5.0 (Rev. 11)
* No changes
7 Series FPGAs Transceivers Wizard (3.6)
* Version 3.6 (Rev. 10)
* General: Improved open_checkpoint runtime by re-writing inefficient get_pins queries.
7 Series Integrated Block for PCI Express (3.3)
* Version 3.3 (Rev. 10)
* Bug Fix: Fixed JTAG debugger Issue.
* Bug Fix: Added waivers for lint errors.
AHB-Lite to AXI Bridge (3.0)
* Version 3.0 (Rev. 13)
* No changes
AMM Master Bridge (1.0)
* Version 1.0 (Rev. 4)
* General: Fixed all the lint issues in the code. Updated example design reset to synchronous reset
* Revision change in one or more subcores
AMM Slave Bridge (1.0)
* Version 1.0 (Rev. 8)
* Revision change in one or more subcores
AXI 1G/2.5G Ethernet Subsystem (7.1)
* Version 7.1 (Rev. 5)
* Bug Fix: Fixed the issue for SGMII over LVDS IO 625MHz clock not connected in the sub block
* Feature Enhancement: Added 2.5G speed support for Artix-7 -2L devices
* Feature Enhancement: Added dummy_port_in in board tab for VCU128 board automation
* Other: Refer to tri_mode_ethernet_mac v9_0 and gig_ethernet_pcs_pma v16_1 core change logs for changes in the sub cores of this core
* Revision change in one or more subcores
AXI AHBLite Bridge (3.0)
* Version 3.0 (Rev. 15)
* General: RTL updated to remove the MAX_FANOUT attribute
AXI APB Bridge (3.0)
* Version 3.0 (Rev. 14)
* No changes
AXI BRAM Controller (4.1)
* Version 4.1
* General: Range calculation added when in multiple master segments
AXI Bridge for PCI Express Gen3 Subsystem (3.0)
* Version 3.0 (Rev. 8)
* General: Updated Subcore version for axi_bram_ctrl to 4.1
* Revision change in one or more subcores
AXI CAN (5.0)
* Version 5.0 (Rev. 21)
* General: Updated Internal XDC
* Revision change in one or more subcores
AXI Central Direct Memory Access (4.1)
* Version 4.1 (Rev. 18)
* Revision change in one or more subcores
AXI Chip2Chip Bridge (5.0)
* Version 5.0 (Rev. 4)
* General: Improved open_checkpoint runtime by re-writing inefficient get_pins queries.
* Revision change in one or more subcores
AXI Clock Converter (2.1)
* Version 2.1 (Rev. 17)
* Revision change in one or more subcores
AXI Crossbar (2.1)
* Version 2.1 (Rev. 19)
* Revision change in one or more subcores
AXI Data FIFO (2.1)
* Version 2.1 (Rev. 17)
* Revision change in one or more subcores
AXI Data Width Converter (2.1)
* Version 2.1 (Rev. 18)
* Revision change in one or more subcores
AXI DataMover (5.1)
* Version 5.1 (Rev. 20)
* General: Enhanced support for IP Integrator
* General: Fixed lint issues
* Revision change in one or more subcores
AXI Direct Memory Access (7.1)
* Version 7.1 (Rev. 19)
* Revision change in one or more subcores
AXI EMC (3.0)
* Version 3.0 (Rev. 18)
* General: removed MAX_FANOUT
* Revision change in one or more subcores
AXI EPC (2.0)
* Version 2.0 (Rev. 21)
* General: removed MAX_FANOUT
* Revision change in one or more subcores
AXI Ethernet Buffer (2.0)
* Version 2.0 (Rev. 19)
* Revision change in one or more subcores
AXI Ethernet Clocking (2.0)
* Version 2.0 (Rev. 2)
* No changes
AXI Ethernet Lite (3.0)
* Version 3.0 (Rev. 16)
* General: This IP will be deprecated from the 2019.1 release onwards. Please contact a Xilinx FAE if you are looking for this IP.
* Revision change in one or more subcores
AXI GPIO (2.0)
* Version 2.0 (Rev. 20)
* General: Removed MAX_FANOUT attribute
* Revision change in one or more subcores
AXI HWICAP (3.0)
* Version 3.0 (Rev. 22)
* Revision change in one or more subcores
AXI IIC (2.0)
* Version 2.0 (Rev. 21)
* General: Updated the coreinfo.yml memory_maps registers with correct values. No Functional changes
* Revision change in one or more subcores
AXI Interconnect (2.1)
* Version 2.1 (Rev. 19)
* Revision change in one or more subcores
AXI Interrupt Controller (4.1)
* Version 4.1 (Rev. 12)
* Feature Enhancement: Added support for interrupt vector extended address with fast interrupt
* Other: Avoid constraint warnings during OOC synthesis
AXI Lite IPIF (3.0)
* Version 3.0 (Rev. 4)
* No changes
AXI MMU (2.1)
* Version 2.1 (Rev. 16)
* Revision change in one or more subcores
AXI Master Burst (2.0)
* Version 2.0 (Rev. 7)
* No changes
AXI Memory Mapped To PCI Express (2.9)
* Version 2.9
* Bug Fix: Fixed AXI BAR parameter propagation issue in IP Integrator design
* Bug Fix: Fixed JTAG debugger Issue
* Feature Enhancement: Added user_link_up output port
* Revision change in one or more subcores
AXI Memory Mapped to Stream Mapper (1.1)
* Version 1.1 (Rev. 17)
* Revision change in one or more subcores
AXI Multi Channel Direct Memory Access (1.0)
* Version 1.0 (Rev. 4)
* Revision change in one or more subcores
AXI Performance Monitor (5.0)
* Version 5.0 (Rev. 20)
* General: updated XDC files as per guidelines to fix XDCB-5 issues
* Revision change in one or more subcores
AXI Protocol Checker (2.0)
* Version 2.0 (Rev. 4)
* General: Added checks 19, 27, 35, 56, 66 (xVALID_STABLE) to the set of checks enabled when LIGHT_WEIGHT==1.
* General: Added Master-side-only checking mode (PC_MASTER_SIDE).
* General: Increased address range of S_AXI register slave to 4kB from 256B to support Auto Assign Address.
* General: Remove max_fanout attributes
* Revision change in one or more subcores
AXI Protocol Converter (2.1)
* Version 2.1 (Rev. 18)
* General: Remove man_fanout attribute. Placer will replicate as necessary.
* Revision change in one or more subcores
AXI Protocol Firewall (1.0)
* Version 1.0 (Rev. 6)
* General: Remove man_fanout attribute. Placer will replicate as necessary.
* Revision change in one or more subcores
AXI Quad SPI (3.2)
* Version 3.2 (Rev. 17)
* General: Internal GUI changes.
* Revision change in one or more subcores
AXI Register Slice (2.1)
* Version 2.1 (Rev. 18)
* General: Remove max_fanout attributes
* Revision change in one or more subcores
AXI Sideband Utility (1.0)
* Version 1.0 (Rev. 2)
* General: Example design support has been added
* Revision change in one or more subcores
AXI SmartConnect (1.0)
* Version 1.0 (Rev. 10)
* Feature Enhancement: Extend max outstanding transactions (NUM_OUTSTANDING) up to 256
* Feature Enhancement: Supports propagation of unmodified sub-sized (narrow) single-beat transactions.
* Revision change in one or more subcores
AXI TFT Controller (2.0)
* Version 2.0 (Rev. 21)
* General: Removed MAX_FANOUT attribute
* General: Updated XDC files as per guidelines to remove XDCB-5 issues
* Revision change in one or more subcores
AXI Timebase Watchdog Timer (3.0)
* Version 3.0 (Rev. 10)
* Feature Enhancement: Removed MAX_FANOUT attribute
* Revision change in one or more subcores
AXI Timer (2.0)
* Version 2.0 (Rev. 20)
* General: Removed MAX_FANOUT attribute
* Revision change in one or more subcores
AXI Traffic Generator (3.0)
* Version 3.0 (Rev. 4)
* General: updated XDC files as per guidelines to fix XDCB-5 issues
* Revision change in one or more subcores
AXI UART16550 (2.0)
* Version 2.0 (Rev. 20)
* General: Removed MAX_FANOUT attribute
* Revision change in one or more subcores
AXI USB2 Device (5.0)
* Version 5.0 (Rev. 19)
* General: Updated XDC files. No Functional changes
* Revision change in one or more subcores
AXI Uartlite (2.0)
* Version 2.0 (Rev. 22)
* General: removed MAX_FANOUT
* Revision change in one or more subcores
AXI Verification IP (1.1)
* Version 1.1 (Rev. 4)
* General: update QOS in user interface Tcl to match AXI meta-data in IP Integrator
* Revision change in one or more subcores
AXI Video Direct Memory Access (6.3)
* Version 6.3 (Rev. 6)
* General: Change done to enable device support. No functional change.
* Revision change in one or more subcores
AXI Virtual FIFO Controller (2.0)
* Version 2.0 (Rev. 20)
* General: subcore AXI BRAM CTRL version changed from v4.0 to v4.1 in example design and No other functional changes.
* Revision change in one or more subcores
AXI-Stream FIFO (4.2)
* Version 4.2
* Feature Enhancement: FIFO generator replaced with XPM.
* Feature Enhancement: Default values for FIFO_PE_THRESHOLD parameters changed to 5.
* Revision change in one or more subcores
AXI4-Stream Accelerator Adapter (2.1)
* Version 2.1 (Rev. 14)
* General: Updated the constraints to improve open_checkpoint runtime. No functional changes
AXI4-Stream Broadcaster (1.1)
* Version 1.1 (Rev. 17)
* General: Product Guide link updated.
* Revision change in one or more subcores
AXI4-Stream Clock Converter (1.1)
* Version 1.1 (Rev. 19)
* General: Project Guide link updated.
* Revision change in one or more subcores
AXI4-Stream Combiner (1.1)
* Version 1.1 (Rev. 16)
* General: Product Guide link updated.
* Revision change in one or more subcores
AXI4-Stream Data FIFO (2.0)
* Version 2.0
* Port Change: Removed m_axis_aresetn port. The FIFO is only reset from the s_axis_aresetn pin on s_axis_aclk domain.
* Port Change: Removed axis_data_count port. Use wr_axis_data_count instead.
* Port Change: Status ports wr_axis_data_count, rd_axis_data_count are now optional.
* Feature Enhancement: Transitioned from FIFO Generator to xpm_fifo_axis.
* Feature Enhancement: Optional ECC support with optional error injection for Block RAM and UltraRAM FIFO types.
* Feature Enhancement: Optional almost empty/full, programmable empty/full status flags added.
* Feature Enhancement: Packet mode now available with independent clocks.
* Other: Product Guide link updated.
* Revision change in one or more subcores
AXI4-Stream Data Width Converter (1.1)
* Version 1.1 (Rev. 17)
* General: Product Guide link updated.
* Revision change in one or more subcores
AXI4-Stream Interconnect (2.1)
* Version 2.1 (Rev. 19)
* General: Product Guide link updated.
* General: Update axis_data_fifo to version v2.0.
* Revision change in one or more subcores
AXI4-Stream Protocol Checker (2.0)
* Version 2.0 (Rev. 2)
* Revision change in one or more subcores
AXI4-Stream Register Slice (1.1)
* Version 1.1 (Rev. 18)
* General: Product Guide link updated.
* Revision change in one or more subcores
AXI4-Stream Subset Converter (1.1)
* Version 1.1 (Rev. 18)
* General: Product Guide link updated.
* Revision change in one or more subcores
AXI4-Stream Switch (1.1)
* Version 1.1 (Rev. 18)
* General: Product Guide link updated.
* Revision change in one or more subcores
AXI4-Stream Verification IP (1.1)
* Version 1.1 (Rev. 4)
* General: update Arm axi4s protocol checker for xsim
* Revision change in one or more subcores
AXI4-Stream to Video Out (4.0)
* Version 4.0 (Rev. 10)
* Bug Fix: Updated YUV420 remapper interrupts which are now tied with remap_en
* Bug Fix: Updated block in IP Integrator to remove polarity bubbles from aclken and vid_io_out_ce
* Revision change in one or more subcores
Accumulator (12.0)
* Version 12.0 (Rev. 12)
* No changes
Adder/Subtractor (12.0)
* Version 12.0 (Rev. 12)
* No changes
Audio Clock Recovery Unit (1.0)
* Version 1.0 (Rev. 1)
* Feature Enhancement: Supports simple Audio Clock Recovery by dividing the Reference Clock
* Feature Enhancement: Supports Audio Clock Recovery using a loop control (FIFO rate control) mechanism
* Other: First Public Release of IP
Audio Formatter (1.0)
* Version 1.0
* New Feature: Supports 2,4,6 or 8 audio channels
* New Feature: Support for independent read and write modes
* New Feature: Supports Interleaved and non-interleaved packaging modes
* New Feature: Supports multiple dataformats with conversion of AES/PCM inputs to AES/PCM outputs
* New Feature: Adds mute data on missing audio channels inputs
* Other: First Release of IP
Aurora 64B66B (11.2)
* Version 11.2 (Rev. 6)
* Bug Fix: Improved performance in streaming mode for GTY devices when neither of UFC/NFC/USER-K is enabled.
* Bug Fix: Corrected bits assignment of TXdiffctrl signal from 4 bits to 5 bits.
* Bug Fix: Updated the display range of RX_PPM_OFFSET to match UltraScale/UltraScale+ FPGAs Data sheet
* Revision change in one or more subcores
Aurora 8B10B (11.1)
* Version 11.1 (Rev. 6)
* General: Improved open_checkpoint runtime by re-writing inefficient get_pins queries.
* General: Updated the display range of RX_PPM_OFFSET to match UltraScale/UltraScale+ FPGAs Data sheet
* Revision change in one or more subcores
Binary Counter (12.0)
* Version 12.0 (Rev. 12)
* No changes
Block Memory Generator (8.4)
* Version 8.4 (Rev. 2)
* Feature Enhancement: Read Latency Support added for URAM when selected through IP Integrator
* Other: Power Calculations disabled for URAM primitives in IP GUI, no functional changes
* Other: Internal device family change, no functional changes
CANFD (2.0)
* Version 2.0
* General: New version of IP with APB and Additional FIFO support in RX path
* Revision change in one or more subcores
CIC Compiler (4.0)
* Version 4.0 (Rev. 13)
* No changes
CORDIC (6.0)
* Version 6.0 (Rev. 14)
* No changes
CPRI (8.9)
* Version 8.9 (Rev. 2)
* Port Change: Added Hard FEC FIFO latency measurement ports.
* Bug Fix: Fixed synchronization control word bit corruptions in FEC cores.
* Bug Fix: Fixed bug introduced in 2018.1 where slave cores caused the link to resync every 10ms.
* Bug Fix: Fixed incorrect line rate and ref clock comments in common wrapper DRP state machine.
* Bug Fix: Removed 12.1Gbps support on -1LV speed grade Zynq UltraScale+ parts, RXUSRCLK & TXUSRCLK max frequency too low.
* Feature Enhancement: Changed Hard FEC rsfec_clk frequency to improve latency measurement.
* Feature Enhancement: Modified Hard FEC wrapper to improve latency measurement.
* Feature Enhancement: Removed CMAC/GT location limitations in Hard FEC cores.
* Other: Updated to use version 2.5 of the UltraScale Plus CMAC (Hard FEC).
* Revision change in one or more subcores
Chroma Resampler (4.0)
* Version 4.0 (Rev. 14)
* Revision change in one or more subcores
Clock Verification IP (1.0)
* Version 1.0 (Rev. 2)
* General: update to set clk_out in master mode
Clocking Wizard (6.0)
* Version 6.0 (Rev. 2)
* Bug Fix: Made input source independent for primary and secondary clock
* Other: New family support added
Color Correction Matrix (6.0)
* Version 6.0 (Rev. 15)
* Revision change in one or more subcores
Color Filter Array Interpolation (7.0)
* Version 7.0 (Rev. 14)
* Revision change in one or more subcores
Compact GT (1.0)
* Version 1.0 (Rev. 4)
* Revision change in one or more subcores
Complex Multiplier (6.0)
* Version 6.0 (Rev. 16)
* General: Support added for new devices. No change to functionality
Concat (2.1)
* Version 2.1 (Rev. 1)
* No changes
Constant (1.1)
* Version 1.1 (Rev. 5)
* No changes
Convolution Encoder (9.0)
* Version 9.0 (Rev. 13)
* No changes
DDR3 SDRAM (MIG) (1.4)
* Version 1.4 (Rev. 6)
* Bug Fix: (Xilinx Answer 71697) The FSVE1156 package allowed incorrect data widths
* Feature Enhancement: Interleave Burst Support added to PHY only designs
* Revision change in one or more subcores
DDR4 SDRAM (MIG) (2.2)
* Version 2.2 (Rev. 6)
* Bug Fix: UltraScale+ AXI TG ECC Example Design fix (synthesis issue only)
* Bug Fix: UltraScale AXI TG undersized WRAP accesses fix
* Bug Fix: (Xilinx Answer 71697) The FSVE1156 package allowed incorrect data widths
* Bug Fix: VREF value for x4 components changed to match x4 DIMM's
* Feature Enhancement: (Xilinx Answer 71696) Added support for changing Refresh Parameters through TCL flow
* Feature Enhancement: Interleave Burst Support added to PHY only designs
* Revision change in one or more subcores
DDS Compiler (6.0)
* Version 6.0 (Rev. 17)
* General: Support for new devices. No change to functionality.
DMA/Bridge Subsystem for PCI Express (PCIe) (4.1)
* Version 4.1 (Rev. 2)
* Bug Fix: Disabled vendor ID change for non PF0 case
* Bug Fix: Fixed MSI-X packet corruption in case Gen2 devices.
* Bug Fix: Added an option in the GUI to enable lane reversal parameter for Gen2 devices
* Bug Fix: Fixed Slot Capabilities register offset for Root Port example design in Bridge mode
* Bug Fix: Fixed Bridge address translation issue for 32bit AXI BAR to 64bit PCIe BAR (when AXI Address width is less than 64)
* Bug Fix: Fixed IP Integrator block automation for vu440 device
* Feature Enhancement: Added Resizable BAR for SDAccel
* Feature Enhancement: Added EROM functionality
* Feature Enhancement: Added Parity option for AXI Bridge mode. Added s_axib_wuser and s_axib_ruser signal when it's enabled
* Feature Enhancement: Added an option in the GUI to select PCIe IDs through ports
* Feature Enhancement: Added an option in the GUI to select FIFO mode or decode mode for MSI interrupt in Root Port Bridge mode
* Feature Enhancement: Added an option in the GUI to select MPSOC Root Port solution in basic page for Bridge Root Port mode
* Feature Enhancement: Added an option in the GUI to enable optional debug ports cfg_current_speed and cfg_negotiated_width
* Revision change in one or more subcores
DSP48 Macro (3.0)
* Version 3.0 (Rev. 16)
* No changes
DUC/DDC Compiler (3.0)
* Version 3.0 (Rev. 14)
* No changes
Debug Bridge (3.0)
* Version 3.0 (Rev. 4)
* General: Supported devices and production status are now determined automatically, to simplify support for future devices
Discrete Fourier Transform (4.1)
* Version 4.1
* General: Support added for point sizes 4, 8, 16, 20, 32, 40, 64, 80, 128, 256
DisplayPort (9.0)
* Version 9.0
* Feature Enhancement: DP1.4 MST, HDCP1.3 Update
* Revision change in one or more subcores
DisplayPort RX Subsystem (2.1)
* Version 2.1 (Rev. 4)
* Bug Fix: AXI-4 Stream video interface made (UG934) compliant and controlled with UG934_COMPLIANCE user parameter for backward compatibility
* Bug Fix: Fix to handle random SDP packet sequence
* Bug Fix: Fix to handle audio packet loss
* Bug Fix: Shortened application example design name to fix Windows OS path length issue
* Revision change in one or more subcores
DisplayPort TX Subsystem (2.1)
* Version 2.1 (Rev. 4)
* Bug Fix: AXI-4 Stream video interface made UG934 compliant and controlled with UG934_COMPLIANCE user parameter for backward compatibility
* Bug Fix: Shortened application example design name to fix Windows OS path length issue
* Revision change in one or more subcores
Distributed Memory Generator (8.0)
* Version 8.0 (Rev. 12)
* No changes
Divider Generator (5.1)
* Version 5.1 (Rev. 14)
* General: Support for new devices. No change to performance or functionality
Double Data Rate Sampling (1.0)
* Version 1.0
* No changes
ECC (2.0)
* Version 2.0 (Rev. 12)
* No changes
ERNIC (1.0)
* Version 1.0
* General: Initial Release
ETRNIC (1.1)
* Version 1.1 (Rev. 1)
* Revision change in one or more subcores
Ethernet PHY MII to Reduced MII (2.0)
* Version 2.0 (Rev. 20)
* General: This IP will be deprecated from 2019.1 release onwards. Please contact Xilinx FAE if you are looking for this IP
* Revision change in one or more subcores
FEC 5G Common Utilities (1.1)
* Version 1.1
* No changes
FIFO Generator (13.2)
* Version 13.2 (Rev. 3)
* Feature Enhancement: None
* Other: Reduced simulation warnings in Behavioral model. No functional changes
* Revision change in one or more subcores
FIR Compiler (7.2)
* Version 7.2 (Rev. 11)
* No changes
Fast Fourier Transform (9.1)
* Version 9.1 (Rev. 1)
* Revision change in one or more subcores
Fiber Channel 32GFC RS-FEC (1.0)
* Version 1.0 (Rev. 8)
* General: Device support for xczu3 series added
* Revision change in one or more subcores
Fixed Interval Timer (2.0)
* Version 2.0 (Rev. 9)
* General: Improved accuracy when using FIT period counter
FlexO 100G RS-FEC (1.0)
* Version 1.0 (Rev. 8)
* General: Device support for xczu3 series added
* Revision change in one or more subcores
Floating-point (7.1)
* Version 7.1 (Rev. 7)
* General: Support for new devices. No change to functionality
* General: Disabled internal debug messaging seen when simulating exponential operator
G.709 FEC Encoder/Decoder (2.4)
* Version 2.4
* General: Feature additions for internal use. No changes to interfaces, form or functionality
* Revision change in one or more subcores
G.975.1 EFEC I.4 Encoder/Decoder (1.0)
* Version 1.0 (Rev. 16)
* General: Support for new devices. No change to behavior or functionality.
G.975.1 EFEC I.7 Encoder/Decoder (2.0)
* Version 2.0 (Rev. 17)
* No changes
Gamma Correction (7.0)
* Version 7.0 (Rev. 15)
* Revision change in one or more subcores
Gamma LUT (1.0)
* Version 1.0 (Rev. 4)
* General: Updated synthesizable example design. For Kintex-7 devices, the video clock frequency has changed from 297 MHz to 200 MHz and the video stream clock has changed from 300 MHz to 200 MHz.
* Revision change in one or more subcores
GMII to RGMII (4.0)
* Version 4.0 (Rev. 7)
* General: Updated constraints for faster constraint processing
HBM IP (1.0)
* Version 1.0 (Rev. 2)
* General: Updated for 2018.3
HDCP (1.0)
* Version 1.0 (Rev. 3)
* No changes
HDCP 2.2 Cipher (1.0)
* Version 1.0 (Rev. 3)
* Bug Fix: Updated the constraint to speed up runtime, no functional update.
HDCP 2.2 Montgomery Modular Multiplier (1.0)
* Version 1.0 (Rev. 2)
* No changes
HDCP 2.2 Random Number Generator (1.0)
* Version 1.0 (Rev. 1)
* No changes
HDCP 2.2 Receiver (1.0)
* Version 1.0 (Rev. 10)
* Revision change in one or more subcores
HDCP 2.2 Transmitter (1.0)
* Version 1.0 (Rev. 10)
* Revision change in one or more subcores
HDMI 1.4/2.0 Receiver (3.0)
* Version 1.1
* No changes
HDMI 1.4/2.0 Receiver Subsystem (3.1)
* Version 3.1 (Rev. 1)
* Bug Fix: Fixed Video Drop (2160p) after running for 15-45 minutes
* Bug Fix: Removed un-used pin (IDT_8T49N241_RST_OUT) in ZCU104
* Bug Fix: Removed overriding of the PSS_REF_CLK for ZCU104
* Feature Enhancement: Added two Interrupt in HDMI TX detecting Video Bridge FIFO status (overflow and underflow)
* Feature Enhancement: Example design supporting core upversion (v_tpg from 7.0 to 8.0)
* Feature Enhancement: Example design supporting core upversion (MicroBlaze from 10.0 to 11.0)
* Feature Enhancement: Added support for XC7Z012S Zynq Device
* Revision change in one or more subcores
HDMI 1.4/2.0 Transmitter (3.0)
* Version 2.0
* No changes
HDMI 1.4/2.0 Transmitter Subsystem (3.1)
* Version 3.1 (Rev. 1)
* Bug Fix: Fixed EDID read failures when HDMI cable length is longer issue
* Bug Fix: Removed un-used pin (IDT_8T49N241_RST_OUT) in ZCU104
* Bug Fix: Removed overriding of the PSS_REF_CLK for ZCU104
* Feature Enhancement: Add example design topology (Pass-through + I2S Audio) for ZCU102 (One system configuration only)
* Feature Enhancement: Added two Interrupt in HDMI TX detecting Video Bridge FIFO status (overflow and underflow)
* Feature Enhancement: Example design supporting core upversion (v_tpg from 7.0 to 8.0)
* Feature Enhancement: Example design supporting core upversion (MicroBlaze from 10.0 to 11.0)
* Feature Enhancement: Added support for XC7Z012S Zynq Device
* Feature Enhancement: HPD detection enhancement
* Revision change in one or more subcores
High Speed SelectIO Wizard (3.5)
* Version 3.5
* New Feature: Added new column "Delay values" in Pin Planning page to access delays for each pin
* New Feature: Added new features "Common Bus Direction" and "Common Signal Type" for each byte group for selecting the respective pin properties easily
* Other: Maximum speed limit for UltraScale+ -1 speed grade devices is increased to 1600Mbps
I2S Receiver (1.0)
* Version 1.0 (Rev. 2)
* Bug Fix: Fixed audio_ch**_ctrl register reads due to width mis-match
* Other: Added support for left justification and right justification words
* Other: Updated Example Design to remove unnecessary I/Os
* Revision change in one or more subcores
I2S Transmitter (1.0)
* Version 1.0 (Rev. 2)
* General: Added support for left justification and right justification words
* General: Updated Example Design to remove unnecessary I/Os
* Revision change in one or more subcores
IBERT 7 Series GTH (3.0)
* Version 3.0 (Rev. 17)
* No changes
IBERT 7 Series GTP (3.0)
* Version 3.0 (Rev. 17)
* No changes
IBERT 7 Series GTX (3.0)
* Version 3.0 (Rev. 17)
* No changes
IBERT 7 Series GTZ (3.1)
* Version 3.1 (Rev. 16)
* Revision change in one or more subcores
IBERT UltraScale GTH (1.4)
* Version 1.4 (Rev. 1)
* Bug Fix: Updated RX PPM values for different line rates
* Revision change in one or more subcores
IBERT UltraScale GTY (1.3)
* Version 1.3 (Rev. 1)
* Bug Fix: Updated RX PPM values for different line rates
* Revision change in one or more subcores
IEEE 802.3 200G RS-FEC (1.0)
* Version 1.0 (Rev. 4)
* General: Device support for xczu3 series added
* Revision change in one or more subcores
IEEE 802.3 25G RS-FEC (1.0)
* Version 1.0 (Rev. 10)
* General: Device support for xczu3 series added
* Revision change in one or more subcores
IEEE 802.3 400G RS-FEC (1.0)
* Version 1.0 (Rev. 4)
* General: Device support for xczu3 series added
* Revision change in one or more subcores
IEEE 802.3 50G RS-FEC (1.0)
* Version 1.0 (Rev. 10)
* General: Device support for xczu3 series added
* Revision change in one or more subcores
IEEE 802.3 Clause 74 FEC (1.0)
* Version 1.0 (Rev. 2)
* General: Device support for xczu3 series added
* Revision change in one or more subcores
IEEE 802.3 Multi-channel 25G RSFEC (1.0)
* Version 1.0
* General: Initial release
IEEE 802.3bj 100G RS-FEC (2.0)
* Version 2.0 (Rev. 2)
* General: Device support for xczu3 series added
* Revision change in one or more subcores
ILA (Integrated Logic Analyzer) (6.2)
* Version 6.2 (Rev. 8)
* General: Supported devices and production status are now determined automatically, to simplify support for future devices
IOModule (3.1)
* Version 3.1 (Rev. 4)
* Feature Enhancement: Added support for interrupt vector extended address with fast interrupt
Image Enhancement (8.0)
* Version 8.0 (Rev. 15)
* Revision change in one or more subcores
In System IBERT (1.0)
* Version 1.0 (Rev. 8)
* General: Updated IP level constraints to reduce generation time of core.
* Revision change in one or more subcores
Interlaken 150G (2.4)
* Version 2.4 (Rev. 2)
* Bug Fix: Added XDC constraints for the tools not to optimize the AXI register map counters
* Other: added new devices support
* Revision change in one or more subcores
Interleaver/De-interleaver (8.0)
* Version 8.0 (Rev. 13)
* Revision change in one or more subcores
JESD204 (7.2)
* Version 7.2 (Rev. 4)
* Feature Enhancement: Implemented new XDC waiver mechanism to mask user visibility of acceptable warnings
* Revision change in one or more subcores
JESD204 PHY (4.0)
* Version 4.0 (Rev. 4)
* Bug Fix: Corrected an issue where the example design would be incorrectly generated if TX or RX is set to JESD204C with 8B10B encoding
* Feature Enhancement: Added internal waivers to mask invalid CDC and DRC violations from the IP user
* Feature Enhancement: Improved constraints for the CPLL CAL block when TX and RX are set to QPLL and Dynamic switching is enabled
* Revision change in one or more subcores
JESD204C (4.0)
* Version 4.0
* Bug Fix: Fixed issue where RX buf_fil_lvl register can report incorrect value
* Bug Fix: Fixed issue with EMB alignment in RX when MB_IN_EMB != 1
* Bug Fix: Fixed issue causing RX error count registers not to clear on read
* Bug Fix: Fixed issue with both TX and RX which could cause misalignment between lanes when a running link is reset
* Bug Fix: Changed TX/RX_CMD bus interfaces to be 32 bits per lane to comply with AXI Streaming specification
* Bug Fix: Fixed issue causing incorrect CRC to be generated
* Bug Fix: Fixed issue with synchronization when not all lanes are enabled
* Feature Enhancement: Enhanced IP Example design
* Other: TBD
* Revision change in one or more subcores
JTAG to AXI Master (1.2)
* Version 1.2 (Rev. 8)
* General: AXI BRAM sub IP reference updated
* Revision change in one or more subcores
LDPC Encoder/Decoder (2.0)
* Version 2.0 (Rev. 2)
* Bug Fix: Correction to memory initialization file generation on Windows.
LMB BRAM Controller (4.0)
* Version 4.0 (Rev. 15)
* No changes
LPDDR3 SDRAM (MIG) (1.0)
* Version 1.0 (Rev. 6)
* General: Changes for 2018.3
* Revision change in one or more subcores
LTE DL Channel Encoder (3.0)
* Version 3.0 (Rev. 14)
* No changes
LTE Fast Fourier Transform (2.0)
* Version 2.0 (Rev. 17)
* Revision change in one or more subcores
LTE PUCCH Receiver (2.0)
* Version 2.0 (Rev. 15)
* Revision change in one or more subcores
LTE RACH Detector (3.1)
* Version 3.1 (Rev. 4)
* General: Fix to config loading behavior to allow bulk loading of config to occur as defined in the datasheet.
* Revision change in one or more subcores
LTE UL Channel Decoder (4.0)
* Version 4.0 (Rev. 15)
* General: Support added for new devices. No change to functionality
Local Memory Bus (LMB) 1.0 (3.0)
* Version 3.0 (Rev. 9)
* No changes
MIPI CSI-2 RX Controller (1.0)
* Version 1.0 (Rev. 8)
* No changes
MIPI CSI-2 RX Subsystem (4.0)
* Version 4.0
* Feature Enhancement: Updated the core to follow latest (UG934) Standard
* Feature Enhancement: Enhancement for CSI v2.0 enablement: Addition of RAW16/RAW20/YUV422_10bit and VCx feature
* Feature Enhancement: Added option to enable MIPI D-PHY HS/ESC timeout registers
* Other: Migrated all the FIFOs to XPM FIFO
* Revision change in one or more subcores
MIPI CSI-2 TX Controller (1.0)
* Version 1.0 (Rev. 4)
* No changes
MIPI CSI-2 TX Subsystem (2.0)
* Version 2.0 (Rev. 4)
* Feature Enhancement: For Effective Pixel width <= 32 , enhanced to support Equal Bandwidth ratio on Input and Output interfaces
* Revision change in one or more subcores
MIPI D-PHY (4.1)
* Version 4.1 (Rev. 2)
* Feature Enhancement: Enhancement to 8 Lanes for MIPI D-PHY RX configuration
* Revision change in one or more subcores
MIPI DSI TX Controller (1.0)
* Version 1.0 (Rev. 7)
* Revision change in one or more subcores
MIPI DSI TX Subsystem (2.0)
* Version 2.0 (Rev. 4)
* Feature Enhancement: Support for Spartan7 devices
* Revision change in one or more subcores
Mailbox (2.1)
* Version 2.1 (Rev. 11)
* General: Avoid constraint warnings during OOC synthesis
Memory Helper Core (1.4)
* Version 1.4
* No changes
Memory Interface Generator (MIG 7 Series) (4.2)
* Version 4.2
* Bug Fix: Resolved Windows 10 GUI crashes when trying to browse to a XDC/UCF file (Xilinx Answer 67168).
* Other: Vivado 2018.3 software support.
* Other: Updated 7 Series MIG GUI for improved Windows 10 support.
MicroBlaze (11.0)
* Version 11.0
* Bug Fix: Output Extended Debug Trace PC when exception occurs correctly. Versions that have this issue: 10.0. Can only occur with area optimization when extended debug trace is enabled.
* Bug Fix: Prevent intermittent loss of Extended Debug Trace data after processor debug halt. Versions that have this issue: 10.0. Can only occur when external debug trace is enabled.
* Bug Fix: Write SLR and SHR correctly independent of previous instruction behavior. Versions that have this issue: 10.0. Can only occur with frequency optimization when stack protection is enabled.
* Feature Enhancement: Updated with 64-bit mode
* Other: Output Extended Debug Trace initial PC after start from first executing instruction instead of current PC
* Other: Added AXI bus interface property HAS_LOCK
MicroBlaze Debug Module (MDM) (3.2)
* Version 3.2 (Rev. 15)
* Feature Enhancement: Added support for AXI Master and LMB extended address
* Feature Enhancement: Automatically set debug interface from connected processors
* Feature Enhancement: Allow serial debug interface with no BSCAN
MicroBlaze MCS (3.0)
* Version 3.0 (Rev. 10)
* General: Updated with latest subcores
* Revision change in one or more subcores
Multiplier (12.0)
* Version 12.0 (Rev. 14)
* No changes
Multiply Adder (3.0)
* Version 3.0 (Rev. 13)
* General: Support added for new devices. No change to functionality
Mutex (2.1)
* Version 2.1 (Rev. 10)
* General: Avoid constraint warnings during OOC synthesis
NVMe Host Accelerator (1.0)
* Version 1.0
* General: First Public Release of IP
PCIe PHY IP (1.0)
* Version 1.0 (Rev. 10)
* Bug Fix: Constraints updated to clean up XDCB-5 warnings
* Bug Fix: Added an option to have GT_COMMON block outside of the IP for UltraScale+ devices
* Bug Fix: Enabled RXdfe* and RXlpm* ports in GTWizard instance for UltraScale devices
* Revision change in one or more subcores
PR AXI Shutdown Manager (1.0)
* Version 1.0
* No changes
PR Bitstream Monitor (1.0)
* Version 1.0
* No changes
Partial Reconfiguration Controller (1.3)
* Version 1.3 (Rev. 1)
* No changes
Partial Reconfiguration Decoupler (1.0)
* Version 1.0 (Rev. 7)
* General: Removed a redundant debug message that appears when parameter propagation occurs
Peak Cancellation Crest Factor Reduction (6.2)
* Version 6.2 (Rev. 1)
* Bug Fix: Fix version register readback from control interface in modes other than having Hard Clipper as PPS.
Polar Encoder/Decoder (1.0)
* Version 1.0 (Rev. 2)
* Feature Enhancement: Change to C model code generation utility function for E less than N
Processor System Reset (5.0)
* Version 5.0 (Rev. 13)
* General: removed equivalent_register_removal
QDRII+ SRAM (MIG) (1.4)
* Version 1.4 (Rev. 6)
* General: Updated for 2018.3
* Revision change in one or more subcores
QDRIV SRAM (MIG) (2.0)
* Version 2.0 (Rev. 6)
* General: Updated for 2018.3
* Revision change in one or more subcores
QDRIV SRAM PHY IP (2.0)
* Version 1.2
* No changes
QSGMII (3.4)
* Version 3.4 (Rev. 5)
* General: Updated constraints to improve constraint processing speed
* Revision change in one or more subcores
Queue DMA Subsystem for PCI Express (PCIe) (3.0)
* Version 3.0
* Bug Fix: Descriptor engine and prefetch engine deadlock: QDMA may get into a deadlock situation where the descriptor engine stops fetching the descriptors due to the back pressure on tm_sts
* Bug Fix: Completion timer issue: When multiple queues are running with a timer based trigger mode, it may lead to some of the timers never expiring
* Bug Fix: Eviction of prefetch descriptors issue: With prefetch enabled, eviction of prefetched descriptors happens improperly and leads to data corruption
* Bug Fix: Credit Coalescing Issue: The credits to the Descriptor Engine need to be coalesced to keep the fetch rate high to support more than 15 simultaneous queues
* Bug Fix: C2H QID0 Issue: When a queue invalidation or certain descriptor error events are reported from Descriptor Engine to Prefetch Engine, it might result in it getting recorded against QID0 instead of the actual QID resulting in packet drop on QID0
* Bug Fix: Fixed tm_dsc_sts_avl bus width
* Feature Enhancement: Outstanding data based request throttling in Streaming H2C Engine: This option can enhance C2H stream performance, using user configurable register at 0xE24
* Feature Enhancement: Added User+Timer+Count trigger mode in C2H Completion Engine
* Feature Enhancement: Added an option in the GUI to enable optional debug ports cfg_current_speed and cfg_negotiated_width
* Feature Enhancement: Added 64 bytes descriptors
* Feature Enhancement: Added 64 bytes C2H Stream completion data width
* Feature Enhancement: Decoupled C2H Completion Qid from C2H Data path
* Feature Enhancement: Modified C2H completion entry format(Added programmable color bit, Added programmable error bit, There is no transfer length information)
* Feature Enhancement: Modified C2H Completion interface
* Feature Enhancement: All Contexts are modified
* Feature Enhancement: Configurable DMA BAR location
* Feature Enhancement: Added ATC support for Address translation
* Feature Enhancement: Flexible MSI-X vector allocation up to 32 per each function with SRIOV disabled and up to 8 when enabled
* Feature Enhancement: MSI-X implementation is made external to Base PCIe IP
* Feature Enhancement: Added legacy interrupt
* Feature Enhancement: Removed QID2VEC and move interrupt info to Queue Context
* Feature Enhancement: Added Tcl option CONFIG.adv_int_usr to enable ports for MSIX interrupt vectors to allow more interrupt vectors than GUI allowed values
* Feature Enhancement: Added Tcl option CONFIG.pfch_cache_depth to modify the prefetch cache depth
* Feature Enhancement: Added GUI option to bring ID ports to IP top-level
* Feature Enhancement: Resource reduction and timing improvement updates
* Revision change in one or more subcores
RAM-based Shift Register (12.0)
* Version 12.0 (Rev. 12)
* No changes
RAMA IP (1.1)
* Version 1.1
* New Feature: Updates for improved linear/multi-pseudo-channel bandwidth.
* Revision change in one or more subcores
RGB to YCrCb Color-Space Converter (7.1)
* Version 7.1 (Rev. 13)
* Revision change in one or more subcores
RLDRAM3 (MIG) (1.4)
* Version 1.4 (Rev. 6)
* Bug Fix: (Xilinx Answer 71697) The FSVE1156 package allowed incorrect data widths
* Bug Fix: (Xilinx Answer 69438) Calibration write DQ/DM deskew fix
* Revision change in one or more subcores
RXAUI (4.4)
* Version 4.4 (Rev. 5)
* General: This IP will be deprecated from 2019.1 release onwards. Please contact a Xilinx FAE if you are looking for this IP.
* Revision change in one or more subcores
Radio over Ethernet Framer (1.0)
* Version 1.0
* General: Initial release
Reed-Solomon Decoder (9.0)
* Version 9.0 (Rev. 15)
* Revision change in one or more subcores
Reed-Solomon Encoder (9.0)
* Version 9.0 (Rev. 14)
* Bug Fix: This revision addresses excessive synthesis times for configurations with a large range of variable symbol counts
* Revision change in one or more subcores
Reset Verification IP (1.0)
* Version 1.0 (Rev. 2)
* General: update core info to add master interface mode for rst_out
SC EXIT (1.0)
* Version 1.0 (Rev. 8)
* Feature Enhancement: Extend max outstanding transactions (NUM_OUTSTANDING) up to 256
* Feature Enhancement: Supports propagation of unmodified sub-sized (narrow) single-beat transactions.
* Feature Enhancement: AXI4-to-AXI3 conversion supports back-to-back transactions.
* Revision change in one or more subcores
SC MMU (1.0)
* Version 1.0 (Rev. 7)
* Feature Enhancement: Extend max outstanding transactions (NUM_OUTSTANDING) up to 256.
* Feature Enhancement: Supports propagation of unmodified sub-sized (narrow) single-beat transactions.
* Revision change in one or more subcores
SC SI_CONVERTER (1.0)
* Version 1.0 (Rev. 7)
* Feature Enhancement: Extend max outstanding transactions (NUM_OUTSTANDING) up to 256.
* Feature Enhancement: Supports propagation of unmodified sub-sized (narrow) single-beat transactions.
* Revision change in one or more subcores
SC SPLITTER (1.0)
* Version 1.0 (Rev. 4)
* Revision change in one or more subcores
SC TRANSACTION_REGULATOR (1.0)
* Version 1.0 (Rev. 8)
* Feature Enhancement: Extend max outstanding transactions (NUM_OUTSTANDING) up to 256
* Other: Remove max_fanout attributes
* Revision change in one or more subcores
SDI RX to Video Bridge (2.0)
* Version 2.0
* No changes
SMPTE SD/HD/3G-SDI (3.0)
* Version 3.0 (Rev. 8)
* No changes
SMPTE UHD-SDI (1.0)
* Version 1.0 (Rev. 6)
* Bug Fix: Enhanced TRS detection logic for 3-G SDI mode
* Other: ST352 insertion into C-stream of channel and controlled through new C_TX_INSERT_C_STR_ST352 user parameter
* Other: ST352 extraction from C-stream of channel
SMPTE UHD-SDI RX (1.0)
* Version 1.0
* No changes
SMPTE UHD-SDI RX SUBSYSTEM (2.0)
* Version 2.0 (Rev. 2)
* New Feature: Extraction of ST352 payload from C-stream in addition to Y-stream, if available
* New Feature: Added support for 32 audio channels
* New Feature: Added support for audio channel status
* New Feature: Added support for audio extract to example design
* Revision change in one or more subcores
SMPTE UHD-SDI TX (1.0)
* Version 1.0
* No changes
SMPTE UHD-SDI TX SUBSYSTEM (2.0)
* Version 2.0 (Rev. 2)
* Bug Fix: Fixed max_delay over-constraint to making it easier to meet timing
* Bug Fix: Changed vid_lock, underflow, overflow and TX_ce_err to be rising edge interrupts
* New Feature: Added Pass-Through example design with Picxo
* Revision change in one or more subcores
SPDIF/AES3 (2.0)
* Version 2.0 (Rev. 20)
* Bug Fix: Resolved CDC Crossing Warnings
* Other: TID width updated to six bits
* Revision change in one or more subcores
SelectIO Interface Wizard (5.1)
* Version 5.1 (Rev. 12)
* No changes
Sensor Demosaic (1.0)
* Version 1.0 (Rev. 4)
* General: Updated synthesizable example design. For Kintex-7 devices, the video clock frequency has changed from 297 MHz to 200 MHz and the video stream clock has changed from 300 MHz to 200 MHz.
* Revision change in one or more subcores
Serial RapidIO Gen2 (4.1)
* Version 4.1 (Rev. 5)
* General: Change in file calls during core generation. No affect on output files.
* Revision change in one or more subcores
SmartConnect AXI2SC Bridge (1.0)
* Version 1.0 (Rev. 7)
* Revision change in one or more subcores
SmartConnect Node (1.0)
* Version 1.0 (Rev. 10)
* Feature Enhancement: Extend max outstanding transactions (NUM_OUTSTANDING) up to 256
* Other: Remove max_fanout attribute.
* Revision change in one or more subcores
SmartConnect SC2AXI Bridge (1.0)
* Version 1.0 (Rev. 7)
* Revision change in one or more subcores
SmartConnect Switchboard (1.0)
* Version 1.0 (Rev. 6)
* General: Remove max_fanout attribute.
* Revision change in one or more subcores
Soft Error Mitigation (4.1)
* Version 4.1 (Rev. 11)
* No changes
Soft-Decision FEC (1.1)
* Version 1.1 (Rev. 2)
* Bug Fix: Correction to memory initialization file generation on Windows.
* Other: Device support for xczu35dr and xczu37dr added
Stream Traffic Manager (1.0)
* Version 1.0
* No changes
Switch Core Top (1.0)
* Version 1.0 (Rev. 6)
* Revision change in one or more subcores
System Cache (4.0)
* Version 4.0 (Rev. 5)
* No changes
System ILA (1.1)
* Version 1.1 (Rev. 4)
* General: Width propagation issue fix
* Revision change in one or more subcores
System Management Wizard (1.3)
* Version 1.3 (Rev. 9)
* General: Internal GUI change. Does not affect users.
* General: Board support added for the IP.
TMR Comparator (1.0)
* Version 1.0 (Rev. 2)
* Revision change in one or more subcores
TMR Inject (1.0)
* Version 1.0 (Rev. 3)
* Feature Enhancement: Added support for extended address inject register
TMR Manager (1.0)
* Version 1.0 (Rev. 4)
* Feature Enhancement: Added input to pause internal watchdog
TMR Soft Error Mitigation Interface (1.0)
* Version 1.0 (Rev. 6)
* General: Updated supported families.
* Revision change in one or more subcores
TMR Voter (1.0)
* Version 1.0 (Rev. 2)
* Bug Fix: Hide unused signals in lockstep mode
* Bug Fix: Propagate BRAM bus masert interface properties
TSN Endpoint Block (1.0)
* Version 1.0 (Rev. 3)
* Revision change in one or more subcores
TSN Tri Mode Ethernet MAC (1.0)
* Version 1.0 (Rev. 3)
* No changes
Time-Aware DMA (1.0)
* Version 1.0 (Rev. 2)
* License Addition
* Revision change in one or more subcores
Timer Sync 1588 (1.2)
* Version 1.2 (Rev. 4)
* No changes
Tri Mode Ethernet MAC (9.0)
* Version 9.0 (Rev. 13)
* Bug Fix: HASH(0x1569e00)
* Bug Fix: Updated constraints to fix XDCB-5 DRC violation
* Bug Fix: Updated GMII clock constraint XDC: Specify master clock when an generated clock are defined
* Other: 2.5 Gbps data-rate mode enabled for Artix-7 -2L devices
UHD-SDI Audio (2.0)
* Version 2.0
* New Feature: Added 32-channel support to Audio Embed & Extract
* New Feature: Added support for 7 Series devices
* New Feature: Modified the architecture to reduce resource utilization
* New Feature: Added provision to select the channel pair for AES channel status extraction
* New Feature: Audio Embed : Added provision to extract 192-bit AES channel status
* New Feature: Audio Embed : Added channel padding logic to support non multiple of 4 channel systems (example 2, 6, 10 etc) by padding 2 mute channels to the last group
* New Feature: Audio Extract : Added clock phase based audio clock recovery in non SD-SDI modes
* New Feature: Audio Extract : Added provision to output audio on single AXI4-S or multiple AXI4-S (each per one audio group)
UHD-SDI GT (1.0)
* Version 1.0 (Rev. 3)
* Bug Fix: Added provision to change TDATA width to either 40 or 20
* Bug Fix: Resolved implementation failure when cmp_gt_st was unconnected
* Bug Fix: Fixed QPLL reference clock connectivity
* New Feature: Added control for PICXO mode
UHD-SDI Video Pattern Generator (1.0)
* Version 1.0 (Rev. 1)
* New Feature: Generated TX Family, Rate & Scan out of the mode selected
UltraScale 100G Ethernet Subsystem (2.4)
* Version 2.4
* Bug Fix: Updated the SDMDATA in the GT common wrapper when the shared logic/GT in example design
* Feature Enhancement: Added GT in example design option for ANLT enabled configuration
* Other: Added watchdog timer to reset the GT
* Other: Updated the constraints declarations in the XDC to remove the XDCB-5 DRCs
* Revision change in one or more subcores
UltraScale FPGA Gen3 Integrated Block for PCI Express (4.4)
* Version 4.4 (Rev. 4)
* Bug Fix: Fixed XDCB-5 warnings
* Revision change in one or more subcores
UltraScale FPGAs Transceivers Wizard (1.7)
* Version 1.7 (Rev. 5)
* Feature Enhancement: Added new transceiver configuration preset options for GTY-DisplayPort_8_1G/ GTH-DisplayPort_8_1G/
* Other: Attribute updates for I Temperature grade devices
* Other: Attribute updates for Q/M Temperature grade devices
* Other: Updated the display range of RX_PPM_OFFSET to match UltraScale/UltraScale+ FPGAs Data sheet
UltraScale Soft Error Mitigation (3.1)
* Version 3.1 (Rev. 9)
* Bug Fix: Resolved (Xilinx Answer 71155). Fixed reported error locations, error injection, query and address translations for VU35P and VU37P
* Other: Added support for Space-Grade Kintex UltraScale devices
UltraScale+ 100G Ethernet Subsystem (2.5)
* Version 2.5
* Bug Fix: Updated the SDMDATA in the GT common wrapper when the shared logic/GT in example design
* Feature Enhancement: Added 100GAUI2 - GTM with KP4 FEC Transcode configuration support
* Feature Enhancement: Added CAUI4 - GTM configuration support
* Feature Enhancement: Added GT in example design option for ANLT enabled configuration
* Other: Added new UltraScale+ devices support
* Other: Added watchdog timer to reset the GT
* Other: Updated the constraints declarations in the XDC to remove the XDCB-5 DRCs
* Revision change in one or more subcores
UltraScale+ PCI Express 4c Integrated Block (1.0)
* Version 1.0 (Rev. 4)
* Feature Enhancement: Added Mark Debug utility in "Add. Debug Options" page
* Feature Enhancement: Added Resizable BAR functionality
* Revision change in one or more subcores
UltraScale+ PCI Express Integrated Block (1.3)
* Version 1.3 (Rev. 4)
* Bug Fix: Disabled vendor ID change for non PF0 case
* Feature Enhancement: Added Mark Debug utility in "Add. Debug Options" page
* Feature Enhancement: Added Resizable BAR functionality
* Revision change in one or more subcores
Universal Serial XGMII Ethernet Subsystem (1.0)
* Version 1.0 (Rev. 4)
* Bug Fix: Corrected clock period value used in set_max_delay constraints on CDC paths
* Bug Fix: Updated constraints to fix XDCB-5 DRC violation
* Bug Fix: Fixed corner case bug: TX PTP buffer read error occurs when a pause frame transmission is requested immediately after transmission of a PTP frame
* Other: Optimized register space: Registers pertaining to IP features not enabled at core generation will not be present
* Revision change in one or more subcores
Utility Reduced Logic (2.0)
* Version 2.0 (Rev. 4)
* No changes
Utility Vector Logic (2.0)
* Version 2.0 (Rev. 1)
* No changes
VIO (Virtual Input/Output) (3.0)
* Version 3.0 (Rev. 19)
* No changes
Video AXI4S Remapper (1.0)
* Version 1.0 (Rev. 10)
* Revision change in one or more subcores
Video Color Space Conversion and Correction (1.0)
* Version 1.0 (Rev. 12)
* General: Added 8k support (8192x4320)
* General: Updated synthesizable example design.
* Revision change in one or more subcores
Video Deinterlacer (5.0)
* Version 5.0 (Rev. 12)
* Revision change in one or more subcores
Video DisplayPort 1.4 RX Subsystem (2.0)
* Version 2.0
* Bug Fix: Changed AXI4-Stream Color Mapping to follow UG934
* Bug Fix: Fixed symbol error counter not getting cleared
* Bug Fix: Shortened application example design name to fix Windows OS path length issue
* Bug Fix: XDCB-5 warnings fixed in XDC constraints
* New Feature: Added HDCP v1.3 support
* New Feature: Added Support for MST up to 4 Streams
* New Feature: Added Support for MST Audio (1 Stream only)
* New Feature: Added UltraScale+ GTYE4 support
* New Feature: Added VCU118 RX-Only example design
* Feature Enhancement: Integrated Audio Interface (I2S) and ACR into application example design
* Feature Enhancement: Added Audio Clock Regeneration Interface
* Revision change in one or more subcores
Video DisplayPort 1.4 TX Subsystem (2.0)
* Version 2.0
* Bug Fix: Changed AXI4-Stream Color Mapping to follow (UG934)
* Bug Fix: Shortened application example design name to fix Windows OS path length issue
* Bug Fix: XDCB-5 warnings fixed in XDC constraints
* Bug Fix: AXI-4 Stream width updated as multiple of 8
* New Feature: Added HDCP v1.3 support
* New Feature: Added Support for MST up to 4 Streams
* New Feature: Added Support for MST Audio (1 Stream only)
* New Feature: Added UltraScale+ GTYE4 support
* New Feature: Added VCU118 TX-Only example design
* Feature Enhancement: Integrated Audio Interface (I2S) and ACR into application example design
* Revision change in one or more subcores
Video Frame Buffer Read (2.1)
* Version 2.1 (Rev. 1)
* General: Updated license section to make IP license free.
* General: Change Resolution to support 8k
* General: Updated Supported IP version numbers in example design Tcl files
* Revision change in one or more subcores
Video Frame Buffer Write (2.1)
* Version 2.1 (Rev. 1)
* General: Updated license section to make IP license free.
* General: Change Resolution to support 8k
* General: Updated Supported IP version numbers in example design Tcl files
* General: Fixing the color formats having 'X'
* General: remove xdcb-5 err
* General: Addressed issue with Negative Slack by rescuing stream clock.
* Revision change in one or more subcores
Video Horizontal Chroma Resampler (1.0)
* Version 1.0 (Rev. 12)
* Revision change in one or more subcores
Video Horizontal Scaler (1.0)
* Version 1.0 (Rev. 12)
* Revision change in one or more subcores
Video In to AXI4-Stream (4.0)
* Version 4.0 (Rev. 9)
* Bug Fix: Updated block in IPI to remove polarity bubbles from aclken
Video Letterbox Engine (1.0)
* Version 1.0 (Rev. 12)
* Revision change in one or more subcores
Video Mixer (3.0)
* Version 3.0 (Rev. 2)
* General: Made IP license free
* General: Updated application to support flushing
* General: Addressed issue with Negative slack
* General: Changed design dependent IP versions
* General: Resolved XDCB-5 parsing error
* General: Resolved YML errors
* General: Added 8k support
* Revision change in one or more subcores
Video Multi-Scaler (1.0)
* Version 1.0
* General: First Release of IP
* General: Supports up to eight outputs
* General: Supports 8K Resolution
* General: Supports 8 bit and 10 bit
* General: Memory based Scaler
Video On Screen Display (6.0)
* Version 6.0 (Rev. 16)
* Revision change in one or more subcores
Video PHY Controller (2.2)
* Version 2.2 (Rev. 2)
* General: DP protocol support added from GTYE4
* General: Added C_TX_Raw_Mode_EN and C_RX_Raw_Mode_EN for DP UltraScale and UltraScale+ devices
* General: Removed TX MMCM instance in DP GTHE4 when TX Buffer Bypass is enabled
* General: Updated the "get_pins" in the XDCs to enhance the Vivado flow
* Revision change in one or more subcores
Video Processing Subsystem (2.0)
* Version 2.0 (Rev. 10)
* General: Updated license section to make IP license free.
* General: Updated Supported IP version numbers in example design Tcl files
* General: Updated changes for example design timing in ttcl.
* General: XDCB-5 Error Resolved.
* General: Addressed issue with Negative Slack by reducing stream clock.
* General: Fixed the VPSS GUI issue.
* Revision change in one or more subcores
Video Scene Change Detection (1.0)
* Version 1.0
* General: First Release of IP
* General: Scene change detection of input video
* General: Uses Only luma information to detect scene change
* General: Supports up to 8 input streams in memory mapped and 1 stream in stream mode
Video Test Pattern Generator (8.0)
* Version 8.0
* General: Added field_id register, fid_in and fid ports
* General: Added 10k resolution support (10328x7760)
* General: Removed license
* Revision change in one or more subcores
Video Timing Controller (6.1)
* Version 6.1 (Rev. 13)
* Bug Fix: Added active lines register to support SD-SDI resolutions which have a different number of active lines per field.
Video Vertical Chroma Resampler (1.0)
* Version 1.0 (Rev. 12)
* Revision change in one or more subcores
Video Vertical Scaler (1.0)
* Version 1.0 (Rev. 12)
* Revision change in one or more subcores
Video to SDI TX Bridge (2.0)
* Version 2.0
* No changes
Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.3)
* Version 4.3 (Rev. 3)
* No changes
Viterbi Decoder (9.1)
* Version 9.1 (Rev. 10)
* General: Support for new devices. No changes to functionality.
XADC Wizard (3.3)
* Version 3.3 (Rev. 6)
* General: Minor changes in attributes. No affect.
XAUI (12.3)
* Version 12.3 (Rev. 5)
* General: This IP will be deprecated from 2019.1 release onwards. Please contact your Xilinx FAE if you are looking for this IP.
* Revision change in one or more subcores
XHMC (1.0)
* Version 1.0 (Rev. 8)
* Bug Fix: Constraint updated to clean up XDCB-5 warnings
* Revision change in one or more subcores
YCrCb to RGB Color-Space Converter (7.1)
* Version 7.1 (Rev. 13)
* Revision change in one or more subcores
ZYNQ UltraScale+ VCU (1.2)
* Version 1.2
* Port Change: NONE
* Bug Fix: Limited VCU generation to Zynq UltraScale+ MPSoC EV parts
* Feature Enhancement: NONE
* Other: Added GUI option to set number of Decoder Streams
* Other: version 1.2
ZYNQ UltraScale+ VCU DDR4 Controller (1.0)
* Version 1.0
* Port Change: NONE
* Bug Fix: NONE
* Feature Enhancement: Initial release
* Feature Enhancement: Supports limited set of x8, and x16 memory devices.
* Feature Enhancement: Supports for Zynq UltraScale+ MPSoC EV series -1e , -2 , -3e parts.
* Feature Enhancement: Supports limited set of 2133, 2400 and 2667 Component/SODIMM memory devices
* Feature Enhancement: Component/SODIMM support for interface width of 64 bits
* Feature Enhancement: JEDEC-compliant DDR4 initialization support
* Feature Enhancement: Support for 5 high performance AXI ports for connecting to decoder 0, decoder 1, MCU, PS and display controller interfaces
* Other: To be used with Zynq UltraScale+ MPSoC VCU IP only
ZYNQ7 Processing System (5.5)
* Version 5.5 (Rev. 6)
* No changes
ZYNQ7 Processing System VIP (1.0)
* Version 1.0 (Rev. 6)
* Revision change in one or more subcores
ZYNQMPSOC Processing System VIP (1.0)
* Version 1.0 (Rev. 4)
* Revision change in one or more subcores
Zynq UltraScale+ MPSoC (3.2)
* Version 3.2 (Rev. 2)
* Bug Fix: 1.DRC to check DDR Actual frequency >= 332MHZ and based on this critical warning is generated.
* Bug Fix: 2.Introduced psu_init_ddr_self_refresh proc in psu_init.c/tcl
* Bug Fix: 3.Enabled DDR high address by default.
* Bug Fix: 4.Fractional clocking issues bug fixes for APU and Video clocks .
* Bug Fix: 5.Manual and Auto modes clocking consistent output issue with same multipliers/divisors fixed.
* Bug Fix: 5.Critical warning is shown when GEM TSU Clock is connected to EMIO and BUFG clock port pair is not looped back.
* Bug Fix: 6.Added parameters to propagate loop back connectivity information of GEM TSU port clk_to_pl_bufg for register configuration.
* Feature Enhancement: 1.USB PHY reset introduced under I/O configuration page.
* Revision change in one or more subcores
Zynq UltraScale+ RF Data Converter (2.1)
* Version 2.1
* Port Change: Added new debug port for powerup state monitoring
* Bug Fix: Fixed DAC minimum sampling rate from 100MHz to 500MHz
* Bug Fix: Fixed issue where Multi Tile Sync could be enabled when interpolation/decimation values did not match
* Bug Fix: Fixed issue where Multi Tile Sync could be enabled when slice 0 in a Tile was not enabled
* Bug Fix: Fixed ADC scaling output factor for Real to Complex configurations
* Bug Fix: Fixed issue where an early state machine restart for one tile could interfere with the operation of another
* Bug Fix: Fixed issue where post-implementation simulations could fail when ADC0 or DAC0 were disabled
* Bug Fix: Fixed issue where reads from the HSCOM_PWR register could get incorrect data
* New Feature: Added support for Multiband
* New Feature: Added support for Real Time NCO changes via dedicated ports
* New Feature: Added counters for unexpected resets in each tile. Values stored in register Tile BaseAddress + 0x38
* New Feature: Added option to modify reference clock divider
* Feature Enhancement: Changed default value of Mixer Type to "Off" from "Bypass"
* Other: Added PLL Summary Tab to GUI
* Other: IP GUI widgets have been updated
* Other: Interpolation/Decimation parameter values have been changed (x4->4 and x8->8)
* Other: Increased the AXI-4Lite timeout by a factor of 4
* Other: Added memory based data stimulus and capture blocks to example design
* Other: Modified demo testbench data generation and checking. Data is now analyzed in the frequency domain
audio_tpg_v1_0 (1.0)
* Version 1.0
* No changes
axi_msg (1.0)
* Version 1.0 (Rev. 4)
* General: Commented redundant code
* Revision change in one or more subcores
axi_sg (4.1)
* Version 4.1 (Rev. 11)
* Revision change in one or more subcores
interrupt_controller (3.1)
* Version 3.1 (Rev. 4)
* No changes
lib_bmg (1.0)
* Version 1.0 (Rev. 11)
* Revision change in one or more subcores
lib_cdc (1.0)
* Version 1.0 (Rev. 2)
* No changes
lib_fifo (1.0)
* Version 1.0 (Rev. 12)
* Revision change in one or more subcores
lib_pkg (1.0)
* Version 1.0 (Rev. 2)
* No changes
lib_srl_fifo (1.0)
* Version 1.0 (Rev. 2)
* No changes
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 54480 | LogiCORE IP JESD204 - Release Notes and Known Issues for Vivado 2013.1 and newer tools | N/A | N/A |
| 68804 | LogiCORE IP JESD204C 核 - 发布说明与已知问题 | N/A | N/A |
| 61911 | LogiCORE IP JESD204 PHY core - Release Notes and Known Issues | N/A | N/A |
| AR# 71806 | |
|---|---|
| 日期 | 12/21/2018 |
| 状态 | Active |
| Type | 版本说明 |
| Tools | |