AR# 72745

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2019.x Vivado Simulation - Known Issues

描述

This answer record lists the known issues for simulation in the Vivado 2019.x releases.

Each known issue includes a link to another answer record that contains additional information on the issue.

解决方案

Outstanding Issues in Vivado 2019.2:

(Xilinx Answer 69355)2017.1 - SDx - File .settings64-SDx.csh does not contain path to "/usr/lib/x86_64-linux-gnu" in LIBRARY_PATH
(Xilinx Answer 72780)2019.1 - Versal IP example designs fails during elaboration when running post-synthesis functional simulation targetting VCS
(Xilinx Answer 72095)Compile Simlib - IP patch installation breaks compile_simlib IP pre-compilation
(Xilinx Answer 73043)2019.2 - aie_xtlm_v1_0_0 library fails to compile in Ubuntu Linux


Issue resolved in Vivado 2019.2:

(Xilinx Answer 72752)Vivado 2019.1 not compiling simulation libraries for zynq_ultra_ps_e_vip_v*
(Xilinx Answer 54005)LogiCORE IEEE 802.3 Multi-Channel 25G RSFEC Core - Simulation issue with Questa Sim
(Xilinx Answer 72601)Vivado 2019.1 - compile_simlib fails for the IP "hdmi_gt_controller_v1_0_0" targetting VCS-MX
(Xilinx Answer 72795)2019.1 compile_simlib - Zynq UltraScale+ sync_ip_v1_0 fails to compile with IES


Outstanding Issues in Vivado 2019.1:

((Xilinx Answer 54005)LogiCORE IEEE 802.3 Multi-Channel 25G RSFEC Core - Simulation issue with Questa Sim
(Xilinx Answer 72752)Vivado 2019.1 not compiling simulation libraries for zynq_ultra_ps_e_vip_v*
(Xilinx Answer 72780)2019.1 - Versal IP example designs fails during elaboration when running post-synthesis functional simulation targeting VCS
(Xilinx Answer 72095)Compile Simlib - IP patch installation breaks compile_simlib IP pre-compilation
(Xilinx Answer 72601)Vivado 2019.1 - compile_simlib fails for the IP "hdmi_gt_controller_v1_0_0" targeting VCS-MX
(Xilinx Answer 72795)2019.1 compile_simlib - Zynq UltraScale+ sync_ip_v1_0 fails to compile with IES
(Xilinx Answer 69355)2017.1 - SDx - File .settings64-SDx.csh does not contain path to "/usr/lib/x86_64-linux-gnu" in LIBRARY_PATH


AR# 72745
日期 11/08/2019
状态 Active
Type 已知问题
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