AR# 72822

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Tactical Patch - GTM Wizard and IBERT IP Updates for Vivado 2019.1.3

描述

The following answer record contains a tactical patch with updates and fixes for the 2019.1.3 release of Vivado for the UltraScale+ GTM Transceivers Wizard (gtm_wizard_ultrascale_v1_0) and UltraScale+ GTM IBERT (ibert_ultrascale_gtm_v1_0) IP cores.

Caution: Both IP cores and each of the Example design files will need to be regenerated with this patch.

解决方案

To apply this tactical patch:

  1. Apply the Vivado 2019.1.3 patch included in AR72822_vivado_2019_1_3_preliminary_rev1.zip
  2. In the Vivado IP Catalog, add the IP Repository included in gtm_2019_1_3_sysmon_patch.zip


The following port additions are included in this tactical patch:


Ports for Temperature sensing, applicable per GTM Wizard IP instance:

  • temperature [9:0] : Input : 10-bit ADC code from SYSMON Temperature Sensor. Valid values must be used at all times when GTM controller is enabled.

The GTM Wizard and GTM IBERT IP integrate the SYSMON instantiation in the example design. Users designing with example designs do not need custom connections to temperature[9:0] ports.

For GTM parent IP designs that do not include SYSMON instantiations in this patch release, users can manually edit and tie off these ports to 0.

However, designs using PAM4 modulation with either 1) less than 12dB insertion loss at Nyquist or 2) line rate greater than 53Gb/s must integrate the SYSMON instantiation and provide valid values to the temperature[9:0] ports.


Ports when Transcoding configurations are enabled in GTM Wizard GUI:

  • gtm_transcode_bypass_rx_core : Reserved port, tie-off to 0; Future enhancement for GTM Switchable Ethernet configurations
  • gtm_transcode_bypass_tx_core : Reserved port, tie-off to 0; Future enhancement for GTM Switchable Ethernet configurations


Ports for each GTM_DUAL selected in GTM Wizard GUI:

GTM Controller utilizes the Integrated KP4 RS-FEC for designs with PAM4 modulation and insertion loss of less than 12dB (as set in GTM Wizard Receiver Advanced Options). 

The GTM wizard example design makes these port connections. No additional connections are needed.

Designs that do not utilize the integrated KP4 RS-FEC for the specified use mode must implement their own KP4 RS-FEC IP to provide equivalent statistic information as described in the RX FEC section in the Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581):

https://www.xilinx.com/support/documentation/user_guides/ug581-ultrascale-gtm-transceivers.pdf


gtm_cntrl_in_fecrx0cwinc           [DUAL_ENABLE*1 -1]: Input: Slice 0 codeword count increment
gtm_cntrl_in_fecrx0uncorrcwinc     [DUAL_ENABLE*1 -1]: Input: Slice 0 uncorrected codeword count increment
gtm_cntrl_in_fecrx1cwinc           [DUAL_ENABLE*1 -1]: Input: Slice 1 codeword count increment
gtm_cntrl_in_fecrx1uncorrcwinc     [DUAL_ENABLE*1 -1]: Input: Slice 1 uncorrected codeword count increment 

gtm_cntrl_in_fecrxln0biterr0to1inc [DUAL_ENABLE*8 -1]: Input: Lane0 bit error count increment (0 corrected to 1)
gtm_cntrl_in_fecrxln0biterr1to0inc [DUAL_ENABLE*8 -1]: Input: Lane0 bit error count increment (1 corrected to 0)
 
gtm_cntrl_in_fecrxln1biterr0to1inc [DUAL_ENABLE*8 -1]: Input: Lane1 bit error count increment (0 corrected to 1)
gtm_cntrl_in_fecrxln1biterr1to0inc [DUAL_ENABLE*8 -1]: Input: Lane1 bit error count increment (1 corrected to 0)
 
gtm_cntrl_in_fecrxln2biterr0to1inc [DUAL_ENABLE*8 -1]: Input: Lane2 bit error count increment (0 corrected to 1)
gtm_cntrl_in_fecrxln2biterr1to0inc [DUAL_ENABLE*8 -1]: Input: Lane2 bit error count increment (1 corrected to 0)
 
gtm_cntrl_in_fecrxln3biterr0to1inc [DUAL_ENABLE*8 -1]: Input: Lane3 bit error count increment (0 corrected to 1)
gtm_cntrl_in_fecrxln3biterr1to0inc [DUAL_ENABLE*8 -1]: Input: Lane3 bit error count increment (1 corrected to 0)
 
gtm_cntrl_in_fectrxln0lock         [DUAL_ENABLE*1 -1]: Input: Lane 0 lock status 
gtm_cntrl_in_fectrxln1lock         [DUAL_ENABLE*1 -1]: Input: Lane 1 lock status
gtm_cntrl_in_fectrxln2lock         [DUAL_ENABLE*1 -1]: Input: Lane 2 lock status
gtm_cntrl_in_fectrxln3lock         [DUAL_ENABLE*1 -1]: Input: Lane 3 lock status

Note: DUAL_ENABLE above is the number of duals selected in the user design.


Ports for Sampled Eye Scan:

Sampled Eye Scan ports were included in the general Vivado 2019.1.3 release. 

For more details, see (Xilinx Answer 72110) - UltraScale+ GTM - Does GTM support Manual EyeScan like GTY and GTH do?


Known issues for this patch:

Setting the Insertion Loss to < 12 dB in the IBERT UltraScale+ GTM IP Wizards Advanced Settings tab causes the IBERT GTM Eye Slicer Plots to fail to display in the Vivado Hardware Manager GUI.  

The IBERT GTM Eye Slicer Plots work as expected when the Insertion Loss is set to >= 12 dB.  This issue will be resolved in the upcoming 2019.2 release.


Issues not covered by this patch:

For all other GTM knowns issues, refer to (Xilinx Answer 72071) - UltraScale+ GTM Transceivers Wizard and IBERT - Master Release Notes and Known Issues

附件

文件名 文件大小 File Type
AR72822_vivado_2019_1_3_preliminary_rev1.zip 4 MB ZIP
gtm_2019_1_3_sysmon_patch.zip 1 MB ZIP
AR# 72822
日期 10/08/2019
状态 Active
Type 综合文章
器件
Tools
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