AR# 75351

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UltraScale+ PCI Express Integrated Block / UltraScale+ PCI Express 4c Integrated Block (Vivado 2020.1) - Tactical Patch to address timing issues and implementation warnings

描述

Version Found:

  • UltraScale+ PCI Express Integrated Block v1.3 (Rev7) [Vivado 2020.1]
  • UltraScale+ PCI Express 4c Integrated Block v1.0 (Rev8) [Vivado 2020.1]

Version Resolved and other Known Issues: (Xilinx Answer 71399) / (Xilinx Answer 65751)

The patch provided with this answer record fixes the following issues:

  • Addresses timing issues and implementation warnings

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

解决方案

This a known issue to be fixed in a future version of the core.

Separate patches for UltraScale+ PCI Express Integrated Block (PCIe4) and UltraScale+ PCI Express 4c Integrated Block (PCIe4c) are included in the zip file attached to this answer record for Vivado 2020.1.

The attached files contain a "readme" file which include installation instructions.

Revision History:

  • 07/13/2020 - Initial Release

附件

文件名 文件大小 File Type
AR75351_Vivado_2020_1_preliminary_rev1.zip 3 MB ZIP
AR# 75351
日期 12/09/2020
状态 Active
Type 已知问题
IP
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