This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) Xilinx Solution Center for PCI ExpressXilinx Forums:
Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
Supported devices can be found in the following locations:
Tactical Patch
The following table provides a list of tactical patches for the UltraScale+ PCI Express 4c Integrated Block core applicable to corresponding Vivado tool versions.
| Answer Record | Core Version (After installing the Patch) | Tool Version |
|---|---|---|
| (Xilinx Answer 76779) | v1.0 (Rev 76779) | 2021.1 |
| (Xilinx Answer 76337) | v1.0 (Rev 76337) | 2020.2 |
| (Xilinx Answer 75835) | v1.0 (Rev 75835) | 2020.1 |
| (Xilinx Answer 75334) | v1.0 (Rev 75334) | 2020.1 |
| (Xilinx Answer 73417) | v1.0 (Rev 73417) | 2019.2 |
| (Xilinx Answer 71498) | v1.0 (Rev 71498) | 2018.2 |
Known and Resolved Issues
The following table provides known issues for the UltraScale+ PCI Express Integrated Block core, starting with v1.0, initially released in Vivado 2017.3.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
| Answer Record | Title | Version Found | Version Resolved |
|---|---|---|---|
| (Xilinx Answer 76779) | Tactical Patch for Issue Fixes:
| Vivado 2021.1 | Not Resolved Yet Tactical Patch Provided |
| (Xilinx Answer 76337) | MSI-X Table Size support for more than 8 vectors | Vivado 2020.2 | Not Resolved Yet Tactical Patch Provided |
| (Xilinx Answer 75835) | get_timing_arcs command results in '0' for PCIe hardblock in VU19P devices | Vivado 2020.1 | Vivado 2020.2 |
| (Xilinx Answer 75334) | Tactical Patch for Issue Fixes:
| Vivado 2020.1 | Not Resolved Yet Tactical Patch Provided |
| (Xilinx Answer 73417) | Tactical Patch for Issue Fixes:
| Vivado 2019.2 | Vivado 2020.1 |
| (Xilinx Answer 71498) | MCP (Multi Cycle Path) Constraints on RQSEQNUM* signal missing for ES1 parts | Vivado 2018.2 | Vivado 2018.3 |
| (Xilinx Answer 71375) | Link does not train in Gen1 design with Refclk at 125MHz and 250MHz speeds | Vivado 2018.1 | Vivado 2018.2 |
Other Information:
| (Xilinx Answer 75490) | Vivado 2020.1.1 - GTYCHK-1 and GTYCHK-2 DRC Violations |
Revision History:
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 73417 | PCI Express Integrated Block (Vivado 2019.2) - CPLL fails to lock in when reference clock is set to 250MHz at Gen1 rate | N/A | N/A |
| AR# 71399 | |
|---|---|
| 日期 | 08/19/2021 |
| 状态 | Active |
| Type | 版本说明 |
| IP | |