2. 技术支持
  3. AR# 7652: CPLD XPLA2- What are the configuration modes of XPLA2 devices?
  4. AR# 76526: PetaLinux 2021.1 - Product Update Release Notes and Known Issues

AR# 76526

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PetaLinux 2021.1 - Product Update Release Notes and Known Issues

描述

This Answer Record acts as the release notes for PetaLinux 2021.1 and contains links to information about resolved issues and updated collateral contained in this release.

解决方案

BSPs supported for the 2021.1 PetaLinux Release

This table contains supported BSPs for MicroBlaze, Zynq-7000, Zynq UltraScale+ MPSoC/RFSoC and Versal devices are available on the Embedded Development download page.

Note: XY - Represents release year, Z - Represents release version.

PlatformVariantBSP NameBSP Description
MicroBlazeAC701xilinx-ac701-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset which contains MicroBlaze Processor, core peripherals IP's such as AXI UARTLITE, AXI 1G/2.5G Ethernet, AXI I2C, AXI GPIO, AXI DDR controller, SPI flash, led_4bits.
  • Software: fs-boot, u-boot, Linux, device-tree, rootfs (minimal packages).
  • Pre-built Images: Ready to test images bitstream, fs-boot, u-boot, Linux kernel, dtb , and rootfs for booting u-boot and Linux.
MicroBlazeKC705xilinx-kc705-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset which contains MicroBlaze Processor, core peripherals IP's such as AXI UARTLITE, AXI 1G/2.5G Ethernet, AXI I2C, AXI GPIO, AXI DDR controller, Linear flash,led_8bits.
  • Software: fs-boot, u-boot, Linux, device-tree, rootfs (minimal packages).
  • Pre-built Images: Ready to test images bitstream, fs-boot, u-boot, Linux kernel, dtb and rootfs for booting u-boot and Linux.
MicroBlazeKCU105xilinx-kcu105-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset which contains MicroBlaze Processor, core peripherals IP's such as AXI UARTLITE,AXI I2C, AXI GPIO, AXI DDR controller, AXI QSPI, led_8bits, and AXI 1G/2.5G Ethernet
  • Software: fs-boot, U-boot, Linux, device-tree, rootfs (minimal packages).
  • Pre-built Images: Ready to test images bitstream, fs-boot, u-boot, Linux kernel, dtb and rootfs for booting u-boot and Linux.
MicroBlazeSP701xilinx-sp701-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset which contains MicroBlaze Processor, core peripherals IP's such as AXI I2C, AXI GPIO, AXI DDR controller, AXI QSPI, AXI UART Lite, led_8bits and AXI 1G/2.5G Ethernet.
  • Software: fs-boot, U-boot, Linux, device-tree, rootfs (minimal packages).
  • Pre-built Images: Ready to test images bitstream, fs-boot, u-boot, Linux kernel, dtb and rootfs for booting u-boot and Linux.
MicroBlazeVCU118xilinx-vcu118-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset which contains MicroBlaze Processor, core peripherals IP's such as AXI I2C, AXI GPIO, AXI DDR controller, AXI QSPI, AXI
  • UART Lite
  • , led_8bits and AXI 1G/2.5G Ethernet.
  • Software: fs-boot, U-boot, Linux, device-tree, rootfs (minimal packages).
  • Pre-built Images: Ready to test images bitstream, fs-boot, u-boot, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Zynq-7000ZC702xilinx-zc702-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset with Zynq-7000 PS block (DDR, UART, SD, QSPI, Ethernet etc.) and AXI GPIO connected with led_4bits.
  • Software: FSBL, U-boot, Linux, device-tree (includes Open AMP), rootfs (minimal packages).
  • Pre-built Images: Ready to test images bitstream, FSBL, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Zynq-7000ZC706xilinx-zc706-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset with Zynq-7000 PS block (DDR, UART, SD, QSPI, Ethernet etc.) and AXI GPIO connected with led_4bits, dip_switches_4bits, gpio_sws_3bits.
  • Software: FSBL, U-boot, Linux, device-tree (includes Open AMP), rootfs (minimal packages).
  • Pre-built Images: Ready to test images bitstream, FSBL, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Zynq-7000Avnet Digilent Zedboardavnet-digilent-zedboard-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset with Zynq-7000 PS block (DDR, UART, SD, QSPI, Ethernet etc.) and AXI GPIO connected with led_8bits, btns_5bits, sws_8bits.
  • Software: FSBL, U-boot, Linux, device-tree (includes Open AMP), rootfs (minimal packages).
  • Pre-built Images: Ready to test images bitstream, FSBL, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Zynq UltraScale+ MPSoCZCU102 production siliconxilinx-zcu102-v20XY.Z-final.bspThis BSP contains:
  • Hardware(Extensible Platform): This design uses Vivado board preset with Zynq UltraScale+ MPSoC PS block (DDR, UART, SD, QSPI, Ethernet, PCIe, DP, USB, SATA etc.)
  • Software: FSBL, PMUFW, ATF, U-boot, Linux, device-tree (includes Open AMP, Xen), ramdisk rootfs(mini rootfs), full rootfs(minimal packages).
  • Pre-built Images: Ready to test images bitstream, FSBL, PMUFW, ATF, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Zynq UltraScale+ MPSoCZCU104 production siliconxilinx-zcu104-v20XY.Z-final.bspThis BSP contains:
  • Hardware(Extensible Platform): This design uses Vivado board preset with Zynq UltraScale+ MPSoC PS block (DDR, UART, SD, QSPI, Ethernet, DP, USB, SATA etc.), VCU DDR4 Controller (PL DDR) and VCU IP.
  • Software: FSBL, PMUFW, ATF, U-boot, Linux, device-tree (includes Open AMP, Xen), vcu-control software, ramdisk rootfs(mini rootfs), full rootfs (minimal packages including additional software packages such as GStreamer, OpenMAX, V4L2, libdrm and vcu-examples).
  • Pre-built Images: Ready to test images bitstream, FSBL, PMUFW, ATF, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Zynq UltraScale+ MPSoCZCU106 production siliconxilinx-zcu106-v20XY.Z-final.bspThis BSP contains:
  • Hardware 1(Extensible Platform): This design uses Vivado board preset with Zynq UltraScale+ MPSoC PS block (DDR, UART, SD, QSPI, Ethernet, PCIe, DP, USB, SATA etc.), VCU DDR4 Controller (PL DDR) and VCU IP.
  • Hardware 2(Extensible Platform): This design uses Vivado board preset with Zynq UltraScale+ MPSoC PS block (DDR, UART, SD, QSPI, Ethernet, PCIe, DP, USB, SATA etc.), VCU DDR4 Controller (New PL DDR part) and VCU IP.
  • Software: FSBL, PMUFW, ATF, U-boot, Linux, device-tree (includes Open AMP, Xen), vcu-control software, ramdisk rootfs(mini rootfs), full rootfs (minimal packages including additional software packages such as GStreamer, OpenMAX, V4L2, libdrm and vcu-examples).
  • Pre-built Images: Ready to test images bitstream, FSBL, PMUFW, ATF, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Zynq UltraScale+ RFSoCZCU111 production siliconxilinx-zcu111-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset with Zynq UltraScale+ RFSoC PS block (DDR, UART, SD, QSPI, Ethernet, DP, USB, SATA etc.) and rf_data_converters, sd_fec_dec, adc_sink, dac_source, axi_gpio, axi_intc IP's.
  • Software: FSBL, PMUFW, ATF, U-boot, Linux, device-tree (includes Open AMP, Xen), rfdc-drivers, ramdisk rootfs(mini rootfs), full rootfs(minimal packages which includes RDFC example applications).
  • Pre-built Images: Ready to test images bitstream, FSBL, PMUFW, ATF, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Zynq UltraScale+ RFSoCZCU1275xilinx-zcu1275-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset with Zynq UltraScale+ RFSoC PS block (DDR, UART, SD, QSPI, Ethernet, DP, USB, SATA etc.) and rf_data_converters, adc_sink, dac_source, axi_gpio, axi_intc IP's.
  • Software: FSBL, PMUFW, ATF, U-boot, Linux, device-tree (includes Open AMP, Xen), rfdc-drivers, ramdisk rootfs(mini rootfs), full rootfs(minimal packages which includes RDFC example applications).
  • Pre-built Images: Ready to test images bitstream, FSBL, PMUFW, ATF, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Zynq UltraScale+ RFSoCZCU1285xilinx-zcu1285-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset with Zynq UltraScale+ RFSoC PS block (DDR, UART, SD, QSPI, Ethernet, DP, USB, SATA etc.) and rf_data_converters, adc_sink, dac_source, axi_gpio, axi_intc IP's.
  • Software: FSBL, PMUFW, ATF, U-boot, Linux, device-tree (includes Open AMP, Xen), rfdc-drivers, ramdisk rootfs(mini rootfs), full rootfs(minimal packages which includes RDFC example applications).
  • Pre-built Images: Ready to test images bitstream, FSBL, PMUFW, ATF, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Zynq UltraScale+ RFSoCZCU208xilinx-zcu208-v20XY.Z-final.bspThis BSP contains:
  • Hardware(Extensible Platform): This design uses Vivado board preset with Zynq UltraScale+ RFSoC PS block (DDR, UART, SD, QSPI, Ethernet etc.) and ADC_DDR_DMA, DAC_DDR_DMA CLOCKING blocks, axi_gpio, IP's.
  • Software: FSBL, PMUFW, ATF, U-Boot, Linux, device-tree (includes open-amp,xen), rfclk, rfdc-drivers, ramdisk rootfs(mini rootfs), full rootfs(minimal packages which includes RFCLK and RDFC example applications).
  • Pre-built Images: Ready to test images bitstream, FSBL, PMUFW, ATF, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Zynq UltraScale+ RFSoCZCU208-SDFECxilinx-zcu208-sdfec-v20XY.Z-final.bspThis BSP contains:
  • Hardware(Extensible Platform): This design uses Vivado board preset with Zynq UltraScale+ RFSoC PS block (DDR, UART, SD, QSPI, Ethernet etc.) with production silicon and AXI stream blocks, Monitor blocks, SD-FEC, and , axi_gpio, AXI intc, IP's.
  • Software: FSBL, PMUFW, ATF, U-Boot, Linux, device-tree (includes open-amp,xen), rfclk, rfdc-drivers, ramdisk rootfs(mini rootfs), full rootfs(minimal packages which includes RFCLK and RDFC example applications).
  • Pre-built Images: Ready to test images bitstream, FSBL, PMUFW, ATF, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Zynq UltraScale+ RFSoCZCU216xilinx-zcu216-v20XY.Z-final.bspThis BSP contains:
  • Hardware(Extensible Platform): This design uses Vivado board preset with Zynq UltraScale+ RFSoC PS block (DDR, UART, SD, QSPI, Ethernet etc.) and ADC_DDR_DMA, DAC_DDR_DMA CLOCKING blocks, axi_gpio, IP's.
  • Software: FSBL, PMUFW, ATF, U-Boot, Linux, device-tree (includes open-amp,xen), rfclk, rfdc-drivers, ramdisk rootfs(mini rootfs), full rootfs(minimal packages which includes RFCLK and RDFC example applications).
  • Pre-built Images: Ready to test images bitstream, FSBL, PMUFW, ATF, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
SOMK26 SOMxilinx-k26-som-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset with Zynq UltraScale+ MPSoC PS block, SOM PS specific and VCU IP.
  • Software: FSBL, PMUFW, ATF, U-boot, Linux, device-tree, vcu-control software, Ramdisk Rootfs (minimal rootfs) ,Full rootfs packages which includes packagegroup-petalinux-som, packagegroup-core-full-cmdline, packagegroup-petalinux-utils, packagegroup-core-tools-debug, packagegroup-petalinux-networking-stack, packagegroup-petalinux-python-modules, packagegroup-petalinux-jupyter.
  • Pre-built Images: Ready to test images bitstream, FSBL, PMUFW, ATF, u-boot, boot.scr, Linux kernel, dtb and rootfs for booting u-boot and Linux.
Versal ACAP(AI Core)VCK190 Production siliconxilinx-vck190-v20XY.Z-final.bspThis BSP contains:
  • Hardware(Extensible Platform): This design uses Vivado board preset with Versal CIPS IP PS block (DDR, UART, SD, QSPI, Ethernet, USB, etc) with production silicon and AIE IP in PL.
  • Vitis AIE Project: Contains .xsa xclbin and aie app and its project workspace.
  • Software: PLM, PSMFW, ATF, U-Boot, Linux, device-tree (includes open-amp, xen), ramdisk rootfs(mini rootfs), full rootfs(minimal packages like TCL, xrt, zocl, python, libstdc++, aie-matrix-multiplication).
  • Pre-built Images: Ready to test images PDI, PLM, PSMFW, ATF, u-boot, boot.scr, Linux kernel, dtb and rootfs booting u-boot and Linux and Xen.
  • OOB Images: These are ready to boot images with rootfs in SD ext4 partition, Out Of the Box demo images includes packages such as packagegroup-petalinux-jupyter, pm-notebooks, openamp-demo-notebooks, python3-ipywidgets.
Versal ACAP(Prime)VMK180 Production siliconxilinx-vmk180-v20XY.Z-final.bspThis BSP contains:
  • Hardware: This design uses Vivado board preset with Versal CIPS IP PS block (DDR, UART, SD, QSPI, Ethernet, USB, etc) with production silicon.
  • Software: PLM, PSMFW, ATF, U-Boot, Linux, device-tree (includes open-amp, xen), ramdisk rootfs(mini rootfs), full rootfs(minimal packages like TCL, python, libstdc++).
  • Pre-built Images: Ready to test images PDI, PLM, PSMFW, ATF, u-boot, boot.scr, Linux kernel, dtb and rootfs booting u-boot and Linux and Xen.
  • OOB Images: These are ready to boot images with rootfs in SD ext4 partition, Out Of the Box demo images includes packages such as packagegroup-petalinux-jupyter, pm-notebooks, openamp-demo-notebooks, python3-ipywidgets.

 

Unified Images supported for the 2021.1 PetaLinux Release

This table contains supported unified images for Zynq-7000 and Zynq UltraScale+ MPSoC/RFSoC and Versa device are available on the Embedded Development download page.

Note: XY - Represents release year, Z - Represents release version.

PlatformSOC VariantTar file NameUnified Image Description
Zynq-7000Allxilinx-zynq-common-v2021.1.tar.gzThis tar file contains:
  • Pre-built Images: Ready to test images such as u-boot.elf, boot.scr, Image, rootfs.ext4, rootfs.manifest, rootfs.tar.gz and sdk.sh
  • README.txt: This readme file describes how to install and use these image files.
Zynq UltraScale+ MPSoC/RFSoCCG, EG, EV, DRxilinx-zynqmp-common-v2021.1.tar.gzThis tar file contains:
  • Pre-built Images: Ready to test images such as bl31.elf, u-boot.elf, boot.scr, Image, rootfs.ext4, rootfs.manifest, rootfs.tar.gz and sdk.sh
  • README.txt: This readme file describes how to install and use these image files.
Versal ACAPAI Core, Primexilinx-versal-common-v2021.1.tar.gzThis tar file contains:
  • Pre-built Images: Ready to test images such as u-boot.elf, boot.scr, Image, rootfs.ext4, rootfs.manifest, rootfs.tar.gz and sdk.sh
  • README.txt: This readme file describes how to install and use these image files.


Note: The "<architecture> sstate-cache" (sstate_<architecture>_2021.1.tar.gz) file can be found on the Xilinx download area along with an associated README file that outlines the procedure to use "sstate cache".

Refer to the attached file "2021.1_PetaLinux_Packages_List" for software package versions tested on host machines, which is required for PetaLinux installation tools.

README for downloads area.

 

PetaLinux 2021.1 contains the following build collateral:

ComponentGit repoGit BranchesGit TagsCommit IDComments
FSBL, PMU Firmware, PLM, PSM Firmwaregit://github.com/Xilinx/embeddedsw.gitxlnx_rel_v2021.1xilinx_v2021.1d37a0e8824182597abf31ac3f1087a5321b33ad7FSBL for Zynq-7000 is at embeddedsw/lib/sw_apps/zynq_fsbl
FSBL for Zynq UltraScale+ is at embeddedsw/lib/sw_apps/zynqmp_fsbl
PMU for Zynq UltraScale+ Firmware is atembeddedsw/lib/sw-apps/zynqmp_pmufw
PLM for Versal ACAP is at embeddedsw/lib/sw-apps/versal_plm
PSM for Versal ACAP Firmware is at embeddedsw/lib/sw-apps/versal_psmfw
Device-treegit://github.com/Xilinx/device-tree-xlnx.gitxlnx_rel_v2021.1xilinx_v2021.1252758eb1f09bd2f85572f6447060636b79367ad 
Linuxgit://github.com/Xilinx/linux-xlnx.gitxlnx_rebase_v5.10xlnx_rebase_v5.10_2021.1c830a552a6c34931352afd41415a2e02cca3310dLinux Kernel rebase version 5.10
U-Bootgit://github.com/Xilinx/u-boot-xlnx.gitxlnx_rebase_v2021.01xlnx_rebase_v2021.01_2021.141fc08b3fe2d78b00fa2ad4438a39e9164fde3bbU-boot Version v2021.01
QEMUgit://github.com/Xilinx/qemu.gitbranch/xilinx-v2021.1xilinx-v2021.1e40b634b24b37fe521bb2857c5e93ee1d30c2e37 
Xengit://github.com/Xilinx/xen.gitxilinx/release-2021.1xilinx-v2021.14bd2da58b5b008f77429007a307b658db9c0f636Xen Version 4.13
ARM-Trusted-Firmware (ATF)git://github.com/Xilinx/arm-trusted-firmware.gitxlnx_rebase_v2.4xlnx_rebase_v2.4_2021.1851523ea2dd34b71be94870cca82c07f776a6a65ATF is based on upstream version 2.4
Yoctogit://github.com/Xilinx/meta-xilinx.git
git://github.com/Xilinx/meta-xilinx-tools.git
git://github.com/Xilinx/meta-petalinux.git
git://github.com/Xilinx/meta-vitis-ai.git		rel-v2021.1No Tagsad6b704acd4cfb210f83aaf48336e37b550da370
ba75a71f64f2e31c2d585011076382683bdbba0b
a4d83c524452b4fcde9ab29260e16cad63d143d6
e7512b1f8342e6b0bb76dd7f87504a612227d89c		Yocto 3.2.0 Gatesgarth
Yocto Manifestsgit://github.com/Xilinx/yocto-manifests.gitrel-v2021.1No Tags2463d97df7a0720e27be9883454df7c8c9578eb5 
qemu-devicetreesgit://github.com/Xilinx/qemu-devicetrees.gitbranch/xilinx-v2021.1xilinx-v2021.1920dab6cdcc16f08daf885cede3593554ddcaef2 
OpenAMPgit://github.com/Xilinx/open-amp.gitxlnx_rel_v2021.1xilinx-v2021.184041fa84d9bc524357b030ebe9a5174b01377bd 
libmetalgit://github.com/Xilinx/libmetal.gitxlnx_rel_v2021.1xilinx-v2021.13c848513f2dd1227fb54010a3f989ddc3c3dbea2 
VCU OpenMax ILgit://github.com/Xilinx/vcu-omx-il.gitxlnx_rel_v2021.1xilinx_v2021.16d14afdef6441b6bc852a4b5fd8e2e5fcde2b62f 
VCU Control Softwaregit://github.com/Xilinx/vcu-ctrl-sw.gitxlnx_rel_v2021.1xilinx_v2021.14cc53d229485e90ec8512ad1012b20d575821a78 
VCU Firmwaregit://github.com/Xilinx/vcu-firmware.gitxlnx_rel_v2021.1xilinx_v2021.173780a2f55a4e9c10de525cdb0335fbb62364217 
VCU Modulesgit://github.com/Xilinx/vcu-modules.gitxlnx_rel_v2021.1xilinx_v2021.1b74f3fad9ba3ba3adf609cf4fff3570f3a1289ff 
GStreamer OpenMax ILgit://github.com/Xilinx/gst-omx.gitxlnx-rebase-v1.16.3xlnx_rebase_v1.16.3_2021.10ff294b7e75a34d72c8b918aa0fc61dad977db1eGStreamer version 1.16.3
GStreamer Plugins-Basegit://github.com/Xilinx/gst-plugins-base.gitxlnx-rebase-v1.16.3xlnx_rebase_v1.16.3_2021.1d1fd9a95fd5a38f3a941ac1821ce36d3b8e624f8 
GStreamer Plugins-Badgit://github.com/Xilinx/gst-plugins-bad.gitxlnx-rebase-v1.16.3xlnx_rebase_v1.16.3_2021.14cdc4b035f4ec8936e7875634a5581d79bedec7b 
GStreamer Plugins-Goodgit://github.com/Xilinx/gst-plugins-good.gitxlnx-rebase-v1.16.3xlnx_rebase_v1.16.3_2021.1f89f5c9e39ced253694adbab18e91fdbab1ac3b6 
GStreamergit://github.com/Xilinx/gstreamer.gitxlnx-rebase-v1.16.3xlnx_rebase_v1.16.3_2021.1cdc91b6ae73ca9d8404cfc54f417bca4a8fb351a 
hdmi-modulesgit://github.com/Xilinx/hdmi-modules.gitrel-v2021.1xilinx_v2021.14682a52a2a7abc0d4a29ef032090ddc81ea46598 
dp-modulesgit://github.com/Xilinx/dp-modules.gitrel-v2021.1No Tags3d9654043ddc6cb6391b46bc9a98e482c98364db 
GPU MALIgit://github.com/Xilinx/mali-userspace-binaries.gitrel-v2021.1xilinx-v2021.1a1a22c9f03b20d8cb70b91727fe51c1db7f4b061 
Bootgengit://github.com/Xilinx/bootgen.gitxlnx-rel-v2021.1xilinx_v2021.134c4313a09dd75cf6ff5b188136e1a077c5b0aa2 
XRTgit://github.com/Xilinx/XRT.git2021.1No Tags0dc9f505a3a910dea96166db7b5df8530b9ae38e 
RunXgit://github.com/Xilinx/runx.gitxilinx/release-2021.1xilinx-v2021.1be8a3ec422dd164f28204a8d6143f712599dee09 
libdfxgit://github.com/Xilinx/libdfx.gitxlnx-rel-v2021.1xilinx_v2021.16aec15214bf59ece3bb13b51d2d26dd899ba9389 
external-hdfgit://github.com/Xilinx/hdf-examples.gitxlnx-rel-v2021.1No Tags9da77b1de79a5ee76a04e3faeab61c6448fc25c1 
ImageBuildergit://github.com/Xilinx/imagebuilder.gitmasterxilinx-v2021.17760210b3c0e4ac29b7a7e5e2daba86f34ca79c2 
GCC    MB compiler version 10.2
ARM 10.2.0

 

2021.1 Release Notes for Open Source components wiki page:

The below page covers details for all of the open source components changes such as New Features and Bug Fixes in a particular release.

 

2021.1 Release pre-built images wiki page:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1884029195/2021.1+Release

2021.1 New Features:

PetaLinux

  • The Zynq MP and Versal PetaLinux BSPs boot to tiny ram based rootfs and the switch to ext based full rootfs. the default rootfs configuration is for full rootfs on ext4.
  • ZCU102, ZCU104 and ZCU106 all have Vitis enabled design and XSA.
  • New BSP's for ZCU670 and VPK120 boards.
  • PetaLinux tool has u-boot distro boot support for MicroBlaze projects.
  • PetaLinux uses bitbake instead of devtool during config by default.

GPU MALI-400

  • None

 

2021.1 Bug Fixes:

PetaLinux

  • None

GPU MALI-400

  • None

Known Issues for 2021.1:

Linux/BaremetalComponentsDescriptionWork-aroundTo be fixed version
LinuxPetaLinuxZynq UltraScale+ MPSoC: How to enable UHS (SD 3.0) support for ZCU102 and ZCU106 evaluation board PetaLinux BSPs(Xilinx Answer 69978)NA
LinuxXSDKZynq UltraScale+ MPSoC: Connecting XSDB to Linux CPU idle(Xilinx Answer 69143)NA
LinuxFSBLZynq UltraScale+ MPSoC: How to achieve SATA performance in Linux(Xilinx Answer 71584)NA
LinuxFSBLZynq UltraScale+ MPSoC: How to make SMMU work with SATA IP(Xilinx Answer 71790)NA
LinuxQEMU2020.2 QEMU Versal and Zynq UltraScale+ MPSoC - Incorrect dummy cycles sent when using GQSPI dual or quad mode byte transfer instead of CS hold time(Xilinx Answer 75599)NA
LinuxQEMUQEMU 2020.2 Versal and Zynq UltraScale+ MPSOC: Incorrect dummy cycle count for Quad I/O read command on Micron flashes(Xilinx Answer 75600)NA
LinuxQEMU2020.2 QEMU Versal and Zynq UltraScale+ MPSoC: QEMU program stops with XSDB(Xilinx Answer 75614)NA
LinuxQEMU2020.2 Versal and Zynq UltraScale+ MPSOC: QEMU GDB unable to catch segfaults(Xilinx Answer 75615)NA
LinuxQEMU2020.2 Versal QEMU: LPD XPPU does not cover TCM(Xilinx Answer 75684)NA
LinuxPMUFW2021.1 and later Ultra96: How to shut down the Ultra96 V1 or V2 boards directly(Xilinx Answer 76583)NA
LinuxYocto2021.x Yocto, PetaLinux: Why do U-boot and the Kernel not show the current build time stamp(Xilinx Answer 76559)NA
LinuxKernel2020.x - 2021.x Linux: Device tree overlay warning messages are observed while loading overlay(Xilinx Answer 76560)NA
LinuxKernel2020.x - 2021.x MicroBlaze: Linux kernel panics when the Enable Write-back Storage Policy option is enabled in a design(Xilinx Answer 76561)2021.2
LinuxDevice-tree2021.1 Ultra96: DisplayPort does not work on Ultra96 boards(Xilinx Answer 76568)2021.2
LinuxDrivers2021.1 Versal ACAP - Linux: Boot fails if "default" PLM/PSM protection configuration is enabled(Xilinx Answer 76570)2021.2
BaremetalDrivers2021.1 Versal ACAP: xospipsv_flash_polled_example read/write errors may be observed(Xilinx Answer 76571)2021.2
LinuxDevice-tree2020.2-2021.1 Versal ACAP: DTG fails to generate the nodes when ILA added to Versal AXI Stream Interface IP(Xilinx Answer 76575)2021.2
BaremetalAIE drivers2021.1 Versal ACAP: AIE Profile Counter has error messages when AIE Trace is used(Xilinx Answer 76591)2021.2
LinuxLibrary2021.1 Zynq UltraScale+ MPSoC: DFX Manager loading an accelerator app was marked as success but it is really not(Xilinx Answer 76593)2021.2
LinuxDrivers
2021.1 Versal ACAP: Linux UART driver supports only 115200 bps with no provision for changing the baud at runtime
(Xilinx Answer 76595)2021.2
LinuxYocto2020.2/2021.1 Versal ACAP: Yocto runqemu command results in error if image size is not a power of 2(Xilinx Answer 76596)2021.2
LinuxDrivers2021.1 Linux: AXI Ethernet driver returns errors for 1000base-x designs(Xilinx Answer 76597)2021.2

附件

文件名 文件大小 File Type
README_content_v2021_1.txt 1 KB TXT
2021.1_PetaLinux_Package_List.xlsx 29 KB XLSX

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
55776 Release Notes and Known Issues for PetaLinux 2013.04 and later tool versions N/A N/A
AR# 76526
日期 06/24/2021
状态 Active
Type 版本说明
器件
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