AR# 76779

描述

Version Found:

• UltraScale+ PCI Express Integrated Block v1.3 (Rev13) [Vivado 2021.1]
• UltraScale+ PCI Express 4c Integrated Block v1.0 (Rev14) [Vivado 2021.1]
• Versal ACAP Integrated Block for PCI Express v1.0 (Rev7) [Vivado 2021.1]

Version Resolved and other Known Issues: (Xilinx Answer 71399) / (Xilinx Answer 65751) / (Xilinx Answer 73083)

The patch provided with this answer record provides the following fix:

• Adds multi-cycle path of 4 on CFGPHYLINKDOWN signal to ease timing

This article is part of the PCI Express Solution Centre

解决方案

This a known issue to be fixed in a future version of the core. 

Separate patches for UltraScale+ PCI Express Integrated Block (PCIe4), UltraScale+ PCI Express 4c Integrated Block (PCIe4c), and Versal ACAP Integrated Block for PCI Express are included in the zip file attached to this answer record for Vivado 2021.1.

For the latest status on the fix in a Vivado release see: (Xilinx Answer 71399) / (Xilinx Answer 65751) / (Xilinx Answer 73083)

The attached files contain a "readme" file which include installation instructions.

Revision History:

• 08/19/2021 - Initial Release

附件