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  3. AR# 37042: Design Assistant for PCI Express - Is 128-bit interface maintained when x8 Gen2 comes up in Gen1 speed?

AR# 37042

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Design Assistant for PCI Express - Is 128-bit interface maintained when x8 Gen2 comes up in Gen1 speed?

描述

When using the Virtex-6 x8 Gen 2 product, if the core trains to Gen 1 speeds, does the 128-bit user interface remain 128 bits?

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.

解决方案

The x8 Gen 2 product always uses the full 128-bit interface regardless of what speed the link trains too. Also see (Xilinx Answer 36075) regarding information about packet straddling on the 128-bit interface.

Revision History
08/13/2010 - Initial Release

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
36075 Design Assistant for PCI Express - 128-bit interface with packet straddling N/A N/A
36049 Design Assistant for PCI Express - TRN User Application Interface Questions N/A N/A
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A
AR# 37042
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
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