The following answer records represent a collection of issues that have been identified in the ISE 13.x design tools and are related to 7 Series FPGAs. There might be issues that are present and are not listed here. If you discover an issue that is not on this list, please open a WebCase with Xilinx Technical Support.
| ISE Design Suite 13.4 |
| General |
| (Xilinx Answer 43347) Kintex-7 FPGA Initial Engineering Sample (ES) Master Answer Record and Known Issues |
| (Xilinx Answer 45696) Kintex-7 - General Engineering Sample (ES) Master Answer Record and Known Issues |
| (Xilinx Answer 44971)7 series XADC - Accuracy of On Chip Reference |
| (Xilinx Answer 45781)7 series XADC - INL specification information |
(Xilinx Answer 41615) 7 series, BitGen (13.2 and later) - "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)" |
| (Xilinx Answer 41685) 7 series - IBIS Model Availability |
| Timing Analysis |
| (Xilinx Answer 45650)12.4 Timing Analysis/Speed Files/7-Series - Can I use newer SPD Files in older software |
| GTX |
| (Xilinx Answer 43339) 7 series Transceiver Software Use Model Changes |
| (Xilinx Answer 45685)7 series FPGAs Transceiver Wizard v1.6 - Known Issues and Release Notes |
| ChipScope |
| (Xilinx Answer 45656)13.4 - Kintex-7 - GTX IBERT - QPLL will notlock at 8 Gb/s line rate when using General ES silicon |
| (Xilinx Answer 45674)13.4 and earlier - Virtex-7 and Kintex-7 - GTX IBERT core with 562.5 MHz refclk may cause map error |
| (Xilinx Answer 45648)13.4 and earlier- Virtex-7/Kintex-7 - Using KC705 or VC705 "Board Configuration Setting" in GTX IBERT uses incorrect I/O Standard for system clock |
| (Xilinx Answer 42464) Kintex-7, ChipScope Pro - IBERT (13.2 and Later) - Kintex-7 Core Limitations and Support for Early Silicon |
| (Xilinx Answer 41262) 13.x ChipScope, CORE Generator - upgrade cores fails when 7 series part is selected |
| MIG |
| (Xilinx Answer 45195) MIG 7 series v1.4 - Release Notes and Known Issues for ISE Design Suite 13.4 |
| BitGen |
| (Xilinx Answer 44103) 13.3 BitGen, 7 series - DriveDONE option is no longer available as a bitstream generation option |
| (Xilinx Answer 44237) 13.3 BitGen, 7 series - DonePipe option is now enabled by default |
| (Xilinx Answer 44635)7 series - 13.x ISE BitGen - EMCCLK Considerations to ensure that the FPGA Completes Startup Sequence |
(Xilinx Answer 45870)ISE 13.4 Bitgen - 7 Series - Unexpectedly long delay through input when using low voltage standard |
| iMPACT |
(Xilinx Answer 46836)13.4 iMPACT - Kintex-7 - XC7K420T patch and Known Issues |
| ISE Design Suite 13.3 |
| General |
| (Xilinx Answer 43347) Kintex-7 FPGA Initial Engineering Sample (ES) Master Answer Record and Known Issues |
| (Xilinx Answer 42660) 13.2/13.3 ISE Design Suite Known Issues - Limited Access for Artix-7 and Virtex-7 XT devices |
| (Xilinx Answer 41615) 7 series, BitGen (13.2 and later) - "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)" |
| (Xilinx Answer 41685) 7 series - IBIS Model Availability |
| GTX |
| (Xilinx Answer 43339) 7 series Transceiver Software Use Model Changes |
| ChipScope |
| (Xilinx Answer 41262) 13.x ChipScope, CORE Generator - Upgrade cores fails when 7 series part is selected |
| (Xilinx Answer 42464) Kintex-7, ChipScope Pro - IBERT (13.2 and Later) - Kintex-7 Core Limitations and Support for Early Silicon |
| (Xilinx Answer 43747) Kintex-7, ChipScope Pro - IBERT (13.2 and later) - IBERT wizard allows use of unsupported line rates with the QPLL for Initial Engineering Sample Silicon |
| MIG |
| (Xilinx Answer 43099) MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 |
| BitGen |
| (Xilinx Answer 44103) 13.3 Bitgen - 7 series - DriveDONE option is no longer available as a bitstream generation option |
| (Xilinx Answer 44237) 13.3 - Bitgen - 7 series - DonePipe option is now enabled by default |
| ISE Design Suite 13.2 |
| General |
| (Xilinx Answer 42660) 13.2 ISE Design Suite Known Issues - Limited Access for Artix-7 and Virtex-7 XT devices |
| (Xilinx Answer 43237) 13.2 ISE - Virtex-7 7XCV485T designs might error out during implementation with routing contention |
| (Xilinx Answer 42948) 13.2 Licensing - ERROR:Security:11 - No 'xc7vx485t' feature was available for 'ISE' |
| GTX |
| (Xilinx Answer 42615) Design Advisory for 7 series FPGA Transceivers - GTX Port Name Changes in ISE 13.2 Software |
| (Xilinx Answer 43339) 7 series GTX Transceiver Software Use Model Changes |
| Block RAM / FIFO |
| (Xilinx Answer 39995) 7 series FPGAs - Built-in Asynchronous FIFO Software Support |
| Constraints |
| (Xilinx Answer 41615) 13.2 BitGen - "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)" |
| ChipScope |
| (Xilinx Answer 42757) 13.2 - IBERT - "ERROR:Bitgen:342" Occurs During Bitstream Generation of Kintex-7 IBERT |
| (Xilinx Answer 41262) 13.x ChipScope, CORE Generator - upgrade cores fails when 7-series part is selected |
| (Xilinx Answer 42757) 13.2 IBERT - "ERROR:Bitgen:342 occurs during bitgen of Kintex-7 IBERT" |
| (Xilinx Answer 42464) 13.2 ChipScope Pro IBERT - Kintex-7 core limitations and support for 1.0 and 1.1 Silicon |
| (Xilinx Answer 42839) 13.2 Kintex-7 GTX IBERT - TXOUT_DIV and RXOUT_DIV set to incorrect values when line rate = 3.125 Gb/s |
| (Xilinx Answer 42857) Kintex-7 GTX IBERT - Using internal system clock source causes error in BitGen |
| (Xilinx Answer 43747) 13.2 - Kintex-7 IBERT GTX Core Allows Some Unsupported Line Rates with QPLL for Initial ES Silicon |
| iMPACT |
| (Xilinx Answer 44421) Design Advisory for 13.2 iMPACT - Incorrect Indirect programming core file is loaded to Kintex-7 leading to potential device damage |
| MIG |
| (Xilinx Answer 41227) MIG 7 series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 |
| IBISWriter |
| (Xilinx Answer 41685) 7 series - IBIS Model Availability |
Additional Information
To find the generic list of known issues for ISE Design Suite 13.x, see the ISE Design Suite 13: Release Notes Guide (UG631). For information on how to download, install, and obtain a license for ISE Design Suite 13.x, see the ISE Design Suite 13: Installation and Licensing Guide (UG798).
Revision History
09/24/2012 - Minor update; no change to content
03/15/2012 - Added link to 46836
01/31/2012 - Updated to add GES and IES known issues
01/13/2012 - Updated for 13.4 release
10/25/2011 - Updated for 13.3 release
10/12/2011 - Added link to 44421
09/22/2011 - Added link to 43747
07/29/2011 - Added link to 39995
07/27/2011 - Added link to 43339
07/26/2011 - Added links to 42944 and 42946
07/21/2011 - Updated with 43237
07/05/2011 - Initial Release
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 51993 | Xilinx 7 Series FPGA Solution Center - Top Issues | N/A | N/A |
| 45934 | Kintex-7 FPGA KC705 Evaluation Kit - Known Issues and Release Notes Master Answer Record | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 43237 | 13.2 ISE Design Suite - Virtex-7 7XCV485T Designs Might Error Out during Implementation with Routing Contention | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 46760 | 7 Series FPGA Design Assistant - Implementation Issues with Fabric | N/A | N/A |
| 46370 | Xilinx 7 系列 FPGA 解决方案中心 | N/A | N/A |
| 42660 | 13.2/13.3 ISE Design Suite Known Issues - Limited Access for Artix-7 and Virtex-7 XT Devices | N/A | N/A |
| 43347 | Kintex-7 FPGA Initial Engineering Sample (ES) - Known Issues Master Answer Record | N/A | N/A |
| 42946 | Kintex-7 FPGA 设计咨询主答复记录 | N/A | N/A |
| 42944 | Virtex-7 FPGA 设计咨询主答复记录 | N/A | N/A |