AR# 51023

描述

This answer record lists known issues for 2012.x Vivado Synthesis.

解决方案

2012.4 Vivado Synthesis Known Issues

(Xilinx Answer 53546) Vivado 2012.x - Vivado Synthesis - Why does Vivado Synthesis generate multiple drivers when a multi-bit register containing a keep or syn_keep attribute is assigned in a bit slice way in more than two process or always block statements?
(Xilinx Answer 53524) Vivado 2012.x - Vivado Synthesis - Does Vivado Synthesis merge multiple registers that are declared separately and used as the output register bus of a DSP48?
(Xilinx Answer 53503) Vivado 2012.x - Vivado Synthesis - Are null ranges supported by Vivado Synthesis?
(Xilinx Answer 53519) Vivado 2012.x - Vivado Synthesis - How does Vivado Synthesis treat KEEP or DONT_TOUCH on a state machine register upon turning on FSM extraction?
(Xilinx Answer 53505) Vivado 2012.x - Vivado Synthesis - Does Vivado Synthesis infer a block RAM on an asynchronous reset output register?
(Xilinx Answer 53507) Vivado 2012.x - Vivado Synthesis - Does Vivado Synthesis infer block RAM for multi-dimensional arrays greater than two dimensions?
(Xilinx Answer 52335) What are the recommended steps to be followed today in order to do bottom-up synthesis using the Vivado Synthesis tool?
(Xilinx Answer 52333) Why does Vivado Synthesis generate "ERROR: [Synth 8-2914] Unsupported RAM template" when more than two clocks are present within a BRAM memory inferring HDL code?
(Xilinx Answer 52331) Does Vivado Synthesis support VHDL record type to model a memory and infer a Block RAM?
(Xilinx Answer 52307) Does Vivado Synthesis support FSM extraction by default?
(Xilinx Answer 52305) Does Vivado Synthesis support LUT combining by default?
(Xilinx Answer 52304) Does Vivado Synthesis support IEEE MATH_REAL and PROPOSED package libraries?
(Xilinx Answer 52303) Does Vivado Synthesis support resettable memory array?
(Xilinx Answer 52301) Does Vivado Synthesis support the READ_CORES option?
(Xilinx Answer 52300) Does Vivado Synthesis support importing functions in System Verilog Interfaces?
(Xilinx Answer 52264) Does Vivado Synthesis support Asymmetric read/write port width BRAM inference?
(Xilinx Answer 46743) Would Vivado Synthesis be able to infer tristate logic in a lower level design when flatten_hierarchy is set to none?
(Xilinx Answer 52086) Split files for VHDL entity and architecture can cause "ERROR: [Synth 8-1940]"
(Xilinx Answer 47454) Vivado Synthesis - Does Vivado synthesis support Verilog Module instantiation in VHDL entity via work library?
(Xilinx Answer 51087) Does Vivado Synthesis tool support physical constraints?
(Xilinx Answer 51088) As part of True Dual Port RAM coding styles, does Vivado Synthesis tool support generate RAMs when both ports are specified in the same always/process block?
(Xilinx Answer 51237) Vivado Synthesis - Recommended use of default statement with no Safe Implementation
(Xilinx Answer 54907) Vivado Synthesis - Incorrect logic is generated when converting an HDL code containing priority-mux into parallel mux as part of optimization
(Xilinx Answer 52302) Does Vivado Synthesis support non-constant (dynamic) range expression?

2012.3 Vivado Synthesis Known Issues

(Xilinx Answer 52335) What are the recommended steps to be followed today in order to do bottom-up synthesis using the Vivado Synthesis tool?
(Xilinx Answer 52333) Why does Vivado Synthesis generate "ERROR: [Synth 8-2914] Unsupported RAM template" when more than two clocks are present within a BRAM memory inferring HDL code?
(Xilinx Answer 52331) Does Vivado Synthesis support VHDL record type to model a memory and infer a Block RAM?
(Xilinx Answer 52307) Does Vivado Synthesis support FSM extraction by default?
(Xilinx Answer 52305) Does Vivado Synthesis support LUT combining by default?
(Xilinx Answer 52304) Does Vivado Synthesis support IEEE MATH_REAL and PROPOSED package libraries?
(Xilinx Answer 52303) Does Vivado Synthesis support resettable memory array?
(Xilinx Answer 52302) Does Vivado Synthesis support non-constant (dynamic) range expression?
(Xilinx Answer 52301) Does Vivado Synthesis support the READ_CORES option?
(Xilinx Answer 52300) Does Vivado Synthesis support importing functions in System Verilog Interfaces?
(Xilinx Answer 52264) Does Vivado Synthesis support Asymmetric read/write port width BRAM inference?
(Xilinx Answer 46743) Would Vivado Synthesis be able to infer tri-state logic in a lower level design when flatten_hierarchy is set to none?
(Xilinx Answer 52086) Split files for VHDL entity and architecture can cause "ERROR: [Synth 8-1940]"
(Xilinx Answer 47454) Vivado Synthesis - Does Vivado synthesis support Verilog Module instantiation in VHDL entity via work library?
(Xilinx Answer 51087) Does Vivado Synthesis tool support physical constraints?
(Xilinx Answer 51088) As part of True Dual Port RAM coding styles, does Vivado Synthesis tool support generate RAMs when both ports are specified in the same always/process block?
(Xilinx Answer 51237) Vivado Synthesis - Recommended use of default statement with no Safe Implementation

2012.3 Vivado Synthesis Resolved Issues

(Xilinx Answer 50130) Vivado Synthesis - Generates a netlist with the same name as the actual RTL design instantiated unimacro module causing simulations to fail
(Xilinx Answer 51163) Vivado Synthesis - MAX_FANOUT Synthesis Attribute not supported for edif netlist files.

2012.2 Vivado Synthesis Known Issues

(Xilinx Answer 47454) Vivado Synthesis - Does Vivado synthesis support Verilog Module instantiation in VHDL entity via work library?
(Xilinx Answer 50130) Vivado Synthesis - Generates a netlist with the same name as the actual RTL design instantiated unimacro module causing simulations to fail
(Xilinx Answer 51087) Does Vivado Synthesis tool support physical constraints?
(Xilinx Answer 51088) As part of True Dual Port RAM coding styles, does Vivado Synthesis tool support generate RAMs when both ports are specified in the same always/process block?
(Xilinx Answer 51163) Vivado Synthesis - MAX_FANOUT Synthesis Attribute not supported for edif netlist files.
(Xilinx Answer 51237) Vivado Synthesis - Recommended use of default statement with no Safe Implementation

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