AR# 54012

描述

The ZC702 Evaluation Kit Checklist is useful to debug board-related issues and to determine if requesting a Boards RMA is the next step.

Before working through the ZC702 Board Debug Checklist, please review (Xilinx Answer 47864) - Zynq-7000 SoC ZC702 Evaluation Kit - Known Issues and Release Notes Master Answer Record.

解决方案

1) Switch / Jumper Settings

2) Board Power

3) Cable detection

4) JTAG Initialization

The following debug steps assume steps 1-4 have been checked and are working:

5) JTAG Configuration

6) QSPI Flash Configuration

7) SD Card

8) XADC

9) DDR3

10) Ethernet

11) Interface Tests

12) Known Issues for ZC702

1) Switch / Jumper Settings

Default Switch & Jumper Settings for the ZC702 are:

Start from a known safe scenario by verifying the default Switch and Jumper settings. You can then set switches / jumpers for your application.

a) DIP Switch SW10 Programmable Logic JTAG Select Switch Default Settings:

b) DIP Switch SW12 GPIO DIP Switch Default Settings:

c) DIP Switch SW15 Default Settings:

d) DIP Switch SW16 5-pole SPDT MIO DIP Switch Default Settings:

e) Default Jumper Settings:

f) PHY Default Interface Mode Settings:

g) Default XADC Jumper Settings:

2) Board Power

Power-ON LEDs: Initial power testing is performed on the bench using the AC-to-DC power adapter provided in the ZC702 Evaluation Kit. The status of Power-ON LEDs is an indication of board health.

a) Check the status of the following LEDs at Power-ON:

b) If these LEDs above are not lit at power on, you may need to reprogram the TI Power Controllers on your board. 

This can be done using the Texas Instruments Fusion Digital Power Manufacturing tool software package, the Texas Instruments USB Interface Adapter EVM, and the appropriate XML script.

For more details, see (Xilinx Answer 37561); and see (Xilinx Answer 56811) for information on the appropriate XML files to be used (these are board-specific).

If you do not have a TI USB Interface Adapter EVM, you can follow the steps in (Xilinx Answer 54022) to order one.  This cable arrives within days and is a vital debug tool.

Ordering the TI USB Interface Adapter EVM and reprogramming the power controllers is an important step in attempting to restore board functionality.

c) If 12V DC Power ON LED (DS14) is not Green, then 12VDC is not being delivered to the ZC702 power input connector. Follow these steps:

If the above steps fail to enable you to restore power to your board, please review the Support Webpage for your available Support options.

3) Cable detection

The ZC702 uses a USB A-to-micro B cable plugged into the ZC702 Digilent USB-to-JTAG module, U23. 

A 14-pin header (J2) for configuration using either a Parallel Cable IV (PC4) or Platform Cable USB II is also provided in parallel. A JTAG 20-pin header is also present at J58.

To ensure you have the ZC702 setup correctly to connect to the cable of your choosing, please see JTAG Programming Option Selection below:

a) USB A-to-micro-B cable

1. Is the cable visible in Device Manager? If the 3 items highlighted in the figure below are visible in Device Manager, this confirms that your USB cable is operational and has been correctly identified.
   
    

2. Are cable drivers loaded correctly? Drivers for this cable should be included in the iMPACT installation. However, if problems are experienced with USB A-to-micro-B cable connection, a Digilent plug-in can be downloaded from the link below:

   For installation, please follow the guidelines in the document provided in the downloaded files: http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,768&Prod=DIGILENT-PLUGIN.

   This plug-in requires Adept systems 2.4 or later for Windows and Adept systems 2.3.9 or later for Linux. Adept software is available from Digilent: http://digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2.

3. Check system properties and environment variables. For information on environment variables, please see (Xilinx Answer 11630).
4. Is the USB port enabled? User can reboot their system to re-initialize the USB buses.
5. Is the latest version of Xilinx tools, supporting this kit, correctly installed? (iMPACT or ChipScope Pro) (For supported SW version information, please see Kit Product Page: ZC702)

   If an issue is suspected with tools installation, please see Installation and Licensing Guide (make sure to use the most recent version of tools, and associated documentation, which supports the ZC702)

6. Is the Operating System (OS) being used Windows 7? If so, please see (Xilinx Answer 41442) and (Xilinx Answer 44397).

If the above steps fail to enable you to connect, please review the Support Webpage for your available Support options.

b) Platform Cable USB II

1. Is the cable visible in Device Manager?
   
    

2. Are the cable drivers loaded correctly? Drivers for this cable should be included in the iMPACT installation. However, if problems are experienced with the Platform Cable USB II connection, please follow the uninstall and reinstall instructions in (Xilinx Answer 44397).
3. Check system properties and environment variables. For information on environment variables, please see (Xilinx Answer 11630).
4. Is the USB port enabled? User can reboot their system to re-initialize the USB buses.
5. Is the latest version of Xilinx tools, supporting this kit, correctly installed? (iMPACT or ChipScope Pro) (For supported SW version information, please see Kit Product Page: ZC702)

   If an issue is suspected with tools installation, please see Installation and Licensing Guide (make sure to use the most recent version of tools, and associated documentation, which supports the ZC702)

6. Is the Operating System (OS) being used Windows 7? If so, please see (Xilinx Answer 41442) and (Xilinx Answer 44397).

If the above steps fail to enable you to connect, please review the Support Webpage for your available Support options.

c) Parallel Cable IV

1. Are the cable drivers loaded correctly? See (Xilinx Answer 9984) for more information.
2. If you receive the following message in iMPACT: 'ERROR: Device Control LPT_WRITE_CMD_BUFFER Failed' see (Xilinx Answer 22293).
3. Note: Parallel Cable IV speed cannot be modified in iMPACT 13.x and 12.x see (Xilinx Answer 41808) for more details.
4. If you cannot establish a connection with the Parallel Cable IV, see (Xilinx Answer 15742).

If the above steps fail to enable you to connect, please review the Support Webpage for your available Support options.

4) JTAG Initialization

The status of the board JTAG chain is checked using Xilinx Tools (iMPACT or ChipScope Pro). To check to see that the JTAG chain is initialized correctly, follow this JTAG initialization Test Case:

a) Remove any FMC cards from ZC702

b) Set the mode switch SW10 for Digilent USB-to-JTAG interface U23:

c) Set SW16 for JTAG mode (00000)

d) Power up ZC702 on the bench

e) Connect the Digilent USB A-to-micro-B cable to the ZC702 through the Digilent onboard USB-to-JTAG configuration logic module - U23

f) Check Digilent device shows up in Device Manager

g) Ensure Xilinx tools (the latest version which supports ZC702) are correctly installed

h) Launch iMPACT - is the cable identified correctly?

1. If not, see section 3. Cable detection above.
2. If yes, but iMPACT did not discover and display the JTAG chain, slow down the cable speed (Output > Cable Setup)
3. If yes, but iMPACT did not discover and display the JTAG chain, and slowing down the cable speed does not resolve the issue, see the following (assumes Digilent USB A-to-micro B cable is plugged into USB-to-JTAG configuration logic module U23):

If the above steps fail to enable you to initialize the JTAG chain, please disconnect the Digilent USB A-to-micro-B cable from the board and PC. Connect the Platform Cable USB to header J2, and connect to your PC.

Ensure Xilinx tools (preferably the latest version of tools that support the ZC702) are correctly installed. Launch iMPACT - is the cable identified correctly?

If the above steps fail to enable you to initialize the JTAG chain, please review the Support Webpage for your available Support options.

5) JTAG Configuration

If the JTAG chain initializes OK, but JTAG configuration fails, check the following:

a) Verify the mode switch settings for JTAG configuration mode:

SW16 for JTAG mode 00000

b) In iMPACT, select a lower cable frequency and re-attempt configuration.

c) In iMPACT, run the Chain Integrity test by selecting Debug -> Chain Integrity Test. iMPACT will assist in the debugging of this scenario by providing insight into where the failing connection in the chain could be.

d) Pulse the PROG push button on the ZC702 (SW4). Pulsing PROG will clear out any problems caused by power up ramp rate issues with the PL.

e) Read back the FPGA Status Register in iMPACT (Debug -> Read Status Register). The information extracted from the Status Register can help determine the stage of configuration and where a failure has occurred. See (Xilinx Answer 24024) for more details.

f) Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center. The Configuration Solution Center is available to address all questions related to Configuration.

If the above steps fail to enable JTAG configuration, please review the Support Webpage for your available Support options.

6) QSPI Flash Configuration

The Quad-SPI Flash memory located at U41 provides 128 Mb of non-volatile storage that can be used for configuration and data storage (PS).

a) To confirm the QSPI interface on the board is working using a known working example design, download and run the ZC702 Restoring Flash Contents Design Files, whichever version is appropriate for your silicon and software version.

It is recommended to always use the latest version of software which supports the ZC702, and the associated version of the ZC702 Restoring Flash Contents Design Files.

Follow the associated PDF. All are available from the ZC702 Example Designs page accessible from Boards and Kits Support tab > Zynq-7000 All Programmable SoC ZC70 Evaluation Kit > Example Designs.

To identify the silicon version of your kit, please see (Xilinx Answer 37579).

b) Read the ZC702 Restoring Flash Contents design document: ZC702 Restoring Flash Contents PDF: xtp183.pdf and follow the instructions therein.

c) If you have loaded an .mcs file into the QSPI flash on the ZC702, and subsequent boot to the XC7Z020 device fails, the following points should be checked:

1. Verify the SW16 switch settings for QSPI mode:

   SW16 for QSPI mode 00010

2. In iMPACT, select a lower cable frequency and re-attempt configuration.
3. Pulse the PROG push button on the ZC702 (SW4), to attempt to reload the FPGA with the configuration image.
4. Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center. The Configuration Solution Center is available to address all questions related to Configuration.

If the above steps fail to enable BPI configuration, please review the Support Webpage for your available Support options.

7) SD Card

An SD card which slots into SD card connector (J64) can be used for PS Configuration by means of a Processor System Boot from SD card. Information about the SD I/O card specification can be found at the SanDisk Corporation or SD Association websites.

a) Verify SD card is inserted correctly into its socket.

b) Verify the SW16 switch settings for SD mode:

SW16 for SD mode 00110

c) Verify the contents of the SD card as follows:

Insert SD card into an SD reader / SD slot in PC monitor and check contents are as intended. Are the files from which to boot located in the root directory?

The SD card will appear as "Removable Disk" on your Computer; an example directory structure, with example contents of an SD card, can be found below:

Having verified the SD card content and the directory structure, eject the SD card correctly as shown below:

If the above steps fail to resolve the issue, please review the Support Webpage for your available Support options.

8) XADC

The XC7Z020 SoC provides an Analog Front End XADC block. The XADC block includes a dual 12-bit, 1 MSPS Analog-to-Digital Converter (ADC) and on-chip sensors.

a) Verify XADC jumper settings - see Section 1. Switch / Jumper Settings, part g, above.

b) Ensure Xilinx tools (latest version which support ZC702) are correctly installed on your machine.

c) To test the XADC interface on the ZC702, use a known working reference design. If you have access to the AMS101 Evaluation Card (shown below) with the ZC702, download and run the Zynq-7000 All Programmable SoC ZC702 AMS Targeted Reference Design (latest version) to check XADC functionality.

Please ensure that you have the correct version of Xilinx tools installed to run this TRD. 

It is recommended to always use the latest version of software, TRD, and associated documentation (7 Series FPGA AMS Targeted Reference Design User Guide).

You can download this Targeted Reference Design, as well as the AMS Evaluator Installer and Documentation for this TRD, from the ZC702 Documentation page.

d) Details on XADC operation can be found in UG480 and UG772. (Be sure to use the most recent version of the document)

If the above steps fail to resolve the XADC issue, please review the Support Webpage for your available Support options.

9) DDR3

If a problem is suspected with DDR3 / MIG, check the following:

a) Ensure DDR3 SODIMM module is inserted correctly.

b) Download and run the ZC702 BIST Design, whichever version is appropriate for your silicon and software version. 

It is recommended to always use the latest version of software which supports the ZC702, and associated version of the ZC702 BIST Design.

Follow the associated PDF. All are available from the ZC702 Example Design page > Zynq-7000 SoC ZC702 Evaluation Kit.

To identify the silicon version of your kit (C or CES), please see (Xilinx Answer 37579).

c) Read the ZC702 BIST design document: ZC702 BIST PDF: xtp180.pdf

d) Review (Xilinx Answer 34243) - Xilinx MIG Solution Center. The Memory Interface Generator (MIG) Solution Center is available to address all questions related to MIG.

If the above steps fail to resolve the DDR3 issue, please review the Support Webpage for your available Support options.

10) Ethernet

a) The ZC702 LwIP Ethernet Design can be used to test Ethernet functionality, and is included as part of the ZC702 BIST Design Files package. This design allows you to send packets which are then echoed back.

To run the LwIP Ethernet Design files, download the ZC702 BIST PDF file and follow carefully the instructions from page 38. 

The ZC702 BIST PDF and ZC702 BIST Design Files are available from the ZC702 Example Designs page > Zynq-7000 SoC ZC702 Evaluation Kit.

To identify the silicon version of your kit (C or CES), please see (Xilinx Answer 37579).

b) Review (Xilinx Answer 38279) - Ethernet IP Solution Center. The Ethernet IP Solution Center is available to address all questions related to the Xilinx solutions for Ethernet IP.

If the above steps fail to resolve the Ethernet issue, please review the Support Webpage for your available Support options.

11) Interface Tests

(Xilinx Answer 54130) - Zynq-7000 SoC ZC702 Evaluation Kit - Interface Test Designs can be run to ensure that the interfaces on the ZC702 are working correctly. 

This answer record forms part of (Xilinx Answer 43748) - Xilinx Boards and Kits Debug Assistant.

If the above tests fail to resolve the issue, please review the Support Webpage for your available Support options.

12) Known Issues for ZC702

All Known Issues for the Zynq-7000 SoC ZC702 Evaluation Kit are listed in (Xilinx Answer 47864) - Zynq-7000 SoC ZC702 Evaluation Kit - Known Issues and Release Notes Master Answer Record.

If the issue you are faced with is not listed in this Answer Record, and debug fails to resolve the issue, please review the Support Webpage for your available Support options.

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