Xilinx Configuration Solution Center
The Configuration Solution Center is available to address all questions related to Configuration.
Whether you are starting a new Configuration Scheme or troubleshooting a Configuration related problem, use the Configuration Solution Center to guide you to the right information.
Other useful Configuration References:
- Xilinx Configuration Forum: A board to discuss Xilinx Configuration related topics including JTAG, SPI, BPI, SelectMap, eFUSE, Tandem, etc.
This board will also include iMPACT and Vivado Device Programmer software related topics. - Design Hubs: Provide introductory material, key concepts, and FAQs on subjects like Partial Reconfiguration, Programming & Debug
设计助手
Xilinx Configuration Solution Center - Configuration Design Assistant
The following answer records cover current known issues as well as commonly asked questions related to configuration.
Note: This answer record is part of the Xilinx Configuration Solution Center (Xilinx Answer 34904)
The Xilinx Configuration Solution Center is available to address all questions related to Configuration.
UltraScale and UltraScale+
| (Xilinx Answer 66570) | UltraScale Architecture Soft Error Mitigation Controller - Guidance for testing with error injection |
| (Xilinx Answer 63609) | UltraScale and UltraScale+ Soft Error Mitigation Controller - Release Notes |
| (Xilinx Answer 63857) | UltraScale External DONE pull-up recommendation |
7 Series
| (Xilinx Answer 57045) | Design Advisory for Artix-7, Kintex-7 - When CFGBVS is set to VCCO of Bank 0, then Banks 14 and 15 are limited to 3.3V or 2.5V for Configuration |
| (Xilinx Answer 44942) | Virtex-7, Kintex-7, Artix-7 FPGA Configuration - BUSY Pin Removal |
| (Xilinx Answer 42543) | 7 Series Configuration - Fallback is disabled by default; Multiboot image does not fallback |
| (Xilinx Answer 43174) | 7 Series - PROGRAM_B pin held Low prior to power-up does not delay configuration |
| (Xilinx Answer 42544) | 7 Series Configuration - When Fallback is enabled, the device status register is always cleared after a failed configuration attempt |
| (Xilinx Answer 41782) | 7 Series - Why is there no longer a recommendation for Thevenin termination on the CCLK pin for configuration? |
| (Xilinx Answer 41298) | SelectIO 7 Series - What power rail supplies the dedicated configuration pins? (MODE pins, JTAG pins etc.) |
| (Xilinx Answer 47449) | Virtex-7 XC7VX690T Initial Engineering Sample (IES) - iMPACT Verify fails and Configuration Readback does not work correctly unless PCIe DRP is instantiated |
| (Xilinx Answer 50489) | 7 Series - ERROR:Bitgen:145 - Why are RS0 and RS1 pins persisted if the design is not using Multiboot and the BitGen ConfigFallback option is not set? |
| (Xilinx Answer 51337) | 7 Series - How can I work around the Fallback limitation for 32-bit addressing in SPI mode? |
| (Xilinx Answer 51473) | 7 Series - Which dual mode configuration pins do the "BitGen -g persist:yes" option apply to on 7 Series devices? |
| (Xilinx Answer 52626) | 7-Series - STARTUPE2_USRCCLK0 ignores first two clock cycles at output |
| (Xilinx Answer 53903) | 7 Series - When the Readback CRC and AES bistream encryption features are both enabled, the Readback CRC requires the ICAP to be included in the design to function |
| (Xilinx Answer 44635) | 7 Series - EMCCLK considerations to ensure the FPGA completes the startup sequence |
Older Architecture
| (Xilinx Answer 32653) | Spartan-3/-3E/-3A/-3AN/-3DSP Families - I/O's glitch during power up or down, or a PROG_B pulse |
| (Xilinx Answer 33575) | Spartan-6 FPGA - JTAG Configuration Setup For Designs Using GTPs |
Vivado Hardware Manager
| (Xilinx Answer 69758) | Vivado: How do I get a standalone version of Vivado Programming Tools to run in the lab? |
| (Xilinx Answer 66440) | Vivado - Linux OS - Digilent and Xilinx USB cable installation check |
| (Xilinx Answer 59128) | Is it possible to (re)install the Xilinx USB/Digilent cable drivers without a full reinstall of Vivado Design Suite? |
| (Xilinx Answer 52881) | Configuration - BitStream Encryption - How to create and program an encrypted bitstream |
| (Xilinx Answer 54939) | 2013.x Vivado, 14.5/6 iMPACT, Flash Programming, ChipScope, PromGen - I do not see iMPACT or ChipScope when I install the Vivado 2013.1 tools |
| (Xilinx Answer 61312) | Non IEEE 1149.3 compliant devices are not recognized in the JTAG chain |
| (Xilinx Answer 66954) | Intermittent configuration failures can occur when the FPGA is power cycled and the programming cable is connected |
| (Xilinx Answer 65328) | 2015.3 Vivado Device Programmer - UltraScale - Direct configuration of RSA Authenticated bitstreams not supported |
| (Xilinx Answer 55660) | Vivado Constraints - How to resolve DRC Warning:[DRC 23-20] Rule violation (CFGBVS-1) Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design |
| (Xilinx Answer 58406) | 2013.2 Hardware Manager - ERROR:[Labtools 27-1974] Mismatch between the design programmed into the device XC7K325T_0 and the probes file |
iMPACT
| (Xilinx Answer 47890) | 14.x iMPACT - Known Issues for the iMPACT 14.x tools |
| (Xilinx Answer 476) | PROMGen - Description of PROM/EEPROM file formats: MCS, EXO, HEX, and others |
| (Xilinx Answer 52881) | Configuration - BitStream Encryption - How to create and program an encrypted bitstream |
| (Xilinx Answer 23174) | PROMGen - Is it possible to convert an MCS file into a BIN (HEX or EXO) file? |
| (Xilinx Answer 16996) | Vivado/ISE - How does the bitstream compress option work (MFWR - Multiple Frame Write Register)? How much compression will be achieved? |
| (Xilinx Answer 14468) | BitGen - Explanation of output files (.bit, .rbt, .bgn, .drc, msk, .ll, .nky, .rba, .rbb, .rbd, .msd, .bin) |
| (Xilinx Answer 36210) | PROMGen - How can file formats be changed or have files bitswapped? |
| (Xilinx Answer 34599) | iMPACT - Status Register read shows all '0' |
| (Xilinx Answer 8902) | iMPACT - What is "IDCODE looping?" |
| (Xilinx Answer 11857) | iMPACT - What is "Initialize Chain"? |
| (Xilinx Answer 24024) | iMPACT - How can the data from the Status Register be used to debug configuration issues? |
| (Xilinx Answer 34909) | iMPACT - What do the different bits in a Status Register Read and BOOTSTS mean? |
| (Xilinx Answer 13529) | iMPACT - "ERROR: iMPACT:583) - '2' The IDCODE read from the device does not match the IDCODE in the BSDL file" |
| (Xilinx Answer 44237) | 13.3 - BitGen - 7 Series - DonePipe option is now enabled by default |
Cables
| (Xilinx Answer 54381) | Xilinx Programming Cables - Platform Cable USB and Parallel Cable IV - Driver install FAQ |
| (Xilinx Answer 54382) | Digilent Programming Cables - Driver Install FAQ |
| (Xilinx Answer 66440) | Vivado - Linux OS - Digilent and Xilinx USB cable installation check |
| (Xilinx Answer 59128) | Is it possible to (re)install the Xilinx USB/Digilent cable drivers without a full reinstall of Vivado Design Suite? |
| (Xilinx Answer 35924) | 10.1, 11.x - ISE - Installation of Cable Drivers for ISE 10.1, 11.x on Windows 7 |
| (Xilinx Answer 20429) | Platform Cable USB - Frequently Asked Questions (FAQs) |
| (Xilinx Answer 44397) | 13.x/14.x iMPACT - Cable Driver Installation - Installation passes on Windows 7 but the Jungo driver Windrvr6 does not operate or appear in the device manager |
| (Xilinx Answer 64361) | Configuration - Cable Driver - The driver of JTAG USB cable cannot be installed in Ubuntu. |
| (Xilinx Answer 54382) | Digilent Programming Cables - Driver Install FAQ |
| (Xilinx Answer 30184) | iMPACT - "WARNING:iMPACT:923) - Cannot find cable, check cable setup" / "Cable connection failed" |
Generic Configuration Solution
| (Xilinx Answer 11433) | JTAG - Do the JTAG pins need external pull-ups? What should I do with unused JTAG pins? |
| (Xilinx Answer 3203) | JTAG - General description of the TAP Controller states |
| (Xilinx Answer 16832) | JTAG - What is a JTAG scan bridge, scan path linker, or JTAG multiplexer/JTAG mux? |
| (Xilinx Answer 42128) | FPGA Configuration - How many clock cycles should I apply to CCLK after DONE has gone High? |
| (Xilinx Answer 50163) | Tandem PROM - What signals are added to my design by using the Tandem PROM solution? |
| (Xilinx Answer 40212) | Configuration FPGA Multiboot - Can I multiboot a master and slave device at the same time in a parallel or slave daisy chain? |
技术文档
Xilinx Configuration Solution Center - Configuration Documentation
Please refer to the following documentation when using Xilinx Configuration Solutions.
Note: This Answer Record is part of the Xilinx Configuration Solution Center (Xilinx Answer 34904)
UltraScale and UltraScale+
| (UG570) | UltraScale Architecture Configuration User Guide |
| (UG575) | Kintex UltraScale and Virtex UltraScale FPGAs Packaging and Pinouts Product Specification |
| (UG974) | UltraScale Architecture Libraries Guide |
| (UG835) | Vivado Design Suite Tcl Command Reference Guide |
| (DS922) | Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics |
| (DS923) | Virtex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics |
| (DS892) | Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics |
| (DS893) | Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics |
| (XAPP1280) | UltraScale FPGA Post-Configuration Access of SPI Flash Memory using STARTUPE3 |
| (XAPP1257) | MultiBoot and Fallback with SPI Flash in UltraScale FPGAs |
| (XAPP1233) | SPI Configuration and Flash Programming in UltraScale FPGAs |
| (XAPP1230) | Configuration Readback Capture in UltraScale FPGAs |
| (XAPP1220) | UltraScale FPGA BPI Configuration and Flash Programming |
| (XAPP1188) | FPGA Configuration from SPI Flash Memory using a Microprocessor |
| (XAPP1267) | Using Encryption and Authentication to Secure an UltraScale/UltraScale+ FPGA Bitstream |
| (XAPP1283) | Internal Programming of BBRAM and eFUSEs |
| (XAPP1282) | UltraScale FPGA Post-Configuration Access of Parallel NOR Flash Memory using STARTUPE3 |
| (XAPP1232) | Bitstream Identification with USR_ACCESS using the Vivado Design Suite |
| (XAPP1191) | SPI Flash Programming including Bitstream Revision Selection |
| (XAPP1098) | Developing Tamper-Resistant Design with UltraScale and UltraScale+ FPGAs |
7 Series
| (UG470) | 7 Series FPGAs Configuration User Guide |
| (UG475) | 7 Series FPGAs Packaging and Pinout Product Specification |
| (UG953) | 7 Series FPGA and Zynq-7000 SoC Libraries Guide |
| (UG835) | Vivado Design Suite Tcl Command Reference Guide |
| (DS181) | Artix-7 FPGA Data Sheet: DC and AC Switching Characteristics |
| (DS182) | Kintex-7 FPGA Data Sheet: DC and AC Switching Characteristics |
| (DS183) | Virtex-7 FPGA Data Sheet: DC and AC Switching Characteristics |
| (XAPP1260) | eFUSE Programming on a Device Programmer |
| (XAPP1247) | MultiBoot with 7 Series FPGAs and SPI |
| (XAPP1246) | MultiBoot with 7 Series FPGAs and BPI |
| (XAPP1239) | Using Encryption to Secure a 7 Series FPGA Bitstream |
| (XAPP1232) | Bitstream Identification with USR_ACCESS using the Vivado Design Suite |
| (XAPP1188) | FPGA Configuration from SPI Flash Memory using a Microprocessor |
| (XAPP1179) | Using Tandem Configuration for PCIe in the Kintex-7 Connectivity TRD |
| (XAPP1084) | Developing Tamper Resistant Designs with Xilinx Virtex-6 and 7 Series FPGAs |
| (XAPP1081) | QuickBoot Method for FPGA Design Remote Update |
| (XAPP733) | Applying MultiBoot and the LogiCORE IP Soft Error Mitigation Controller |
| (XAPP587) | BPI Fast Configuration and iMPACT Flash Programming with 7 Series FPGAs |
| (XAPP586) | Using SPI Flash with 7 Series FPGAs |
| (XAPP583) | Using a Microprocessor to configure 7 Series FPGAs via Slave Serial or Slave SelectMAP Mode |
| (XAPP497) | Bitstream Identification with USR_ACCESS |
Older Architectures
| (Xilinx Answer 37249) | Xilinx Configuration Solution Center - Documentation - Older Architectures |
Vivado Hardware Manager
| (UG908) | Vivado Design Suite User Guide: Programming and Debugging |
| (UG835) | Vivado Design Suite Tcl Command Reference Guide |
| (UG909) | Vivado Design Suite User Guide: Partial Reconfiguration |
| (UG947) | Vivado Design Suite Tutorial: Partial Reconfiguration |
| (UG936) | Vivado Design Suite Tutorial: Programming and Debugging |
| (UG949) | UltraFast Design Methodology Guide for the Vivado Design Suite |
iMPACT & Cables
| iMPACT Help | |
| (UG344) | USB Cable Installation Guide |
| (DS300) | Platform Cable USB Product Specification |
| (DS593) | Platform Cable USB II Data Sheet |
Note: When reviewing any of the documentation in this Xilinx Answer Record, ensure that the most recent version is being reviewed.
设计咨询
Xilinx 配置解决方案中心 — 配置设计咨询
配置设计咨询答复记录 (DAAR) 的创建主要针对对当前正在进行的设计非常重要的问题，您可以对其进行选项，以纳入 Xilinx 提示通知系统。
注：更新您的 Xilinx 提示通知首选项，请访问：//m.alegre-web.com/support/myalerts。
本答复记录是 Xilinx 配置解决方案中心的一部分 （Xilinx 答复 34904）
UltraScale 与 UltraScale+：
如欲查看 UltraScale FPGA 设计咨询的综合列表，请参见下列主答复记录链接
| (Xilinx Answer 61598) | Kintex UltraScale FPGA 的设计咨询主答复记录 |
| (Xilinx 答复 61930) | Virtex UltraScale FPGA 的设计咨询主答复记录 |
UltraScale 与 UltraScale+：
| 2017 年 4 月 10 日发布的设计咨询提醒: | |
| (Xilinx 答复 68832) | 采用 Vivado 2016.4（或更早版本）进行 UltraScale FPGA、UltraScale+ FPGA 以及 Zynq UltraScale+ MPSoC eFUSE 编程的设计咨询 |
| 2016 年 12 月 19 日发布的设计咨询提醒 | |
| (Xilinx 答复 67645) | 有关 7 系列和 UltraScale 架构 FPGA 配置回退和 POST_CRC limitation 限制的设计咨询 |
| 2016 年 11 月 1 日发布的设计咨询提醒 | |
| (Xilinx 答复 68006) | Xilinx 设计工具（Vivado、SDAccel、SDSoC）2016.1 和 2016.2 write_bitstream 的设计咨询 — 多线程可能会导致配置存储器单元设置不正确 |
| 2015 年 12 月 21 日发布的设计咨询提醒
|
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| (Xilinx 答复65792) | 有关 UltraScale RSA 认证的设计咨询 - 当使用较小的配置接口宽度时，使用 RSA 身份验证的 UltraScale 器件将使比特流身份验证失效。 |
| 2014 年 11 月 10 日发布的设计咨询提醒 | |
| (Xilinx 答复 62631) | 面向 Vivado 2014.3 的设计咨询 – 针对 7 系列和 Ultrascale FPGA 的编程 eFUSE 寄存器操作失败 |
7 系列:
如欲查看 7 系列 FPGA 设计咨询的综合列表，请参见下列主答复记录链接
| (Xilinx 答复 42944) | Virtex-7 FPGA 的设计咨询主答复记录 |
| (Xilinx 答复 42946) | Kintex-7 FPGA 的设计咨询主答复记录 |
| (Xilinx 答复 51456) | Artix-7 FPGA 的设计咨询主答复记录 |
Virtex-7 配置专用设计咨询：
| 2016 年 12 月 19 日发布的设计咨询提醒 | |
| (Xilinx 答复 67645) | 有关 7 系列和 UltraScale 架构 FPGA 配置回退和 POST_CRC limitation 限制的设计咨询 |
| 2014 年 11 月 10 日发布的设计咨询提醒 | |
| (Xilinx 答复 62631) | 面向 Vivado 2014.3 的设计咨询 – 针对 7 系列和 Ultrascale FPGA 的编程 eFUSE 寄存器操作失败 |
| 2012 年 11 月 5 日发布的设计咨询提醒 | |
| (Xilinx 答复 52193) | 7 系列 BPI 多重引导设计咨询 – 当出现回退时，闪存访问总是处于 BPI 异步模式 |
| 2012 年 8 月 20 日发布的设计咨询提醒 | |
| (Xilinx 答复 50906) | 生产 Kintex-7 325T、410T 和 Virtex-7 485XT 的设计咨询 — GES 与生产器件间的比特流兼容性需求 |
Kintex-7 配置专用设计咨询
| 2016 年 12 月 19 日发布的设计咨询提醒 | |
| (Xilinx 答复 67645) | 有关 7 系列和 UltraScale 架构 FPGA 配置回退和 POST_CRC limitation 限制的设计咨询 |
| 2014 年 11 月 10 日发布的设计咨询提醒 | |
| (Xilinx 答复 62631) | 面向 Vivado 2014.3 的设计咨询 – 针对 7 系列和 Ultrascale FPGA 的编程 eFUSE 寄存器操作失败 |
| 2013 年 4 月 3 日发布的设计咨询提醒 | |
| (Xilinx 答复 50906) | 针对生产 Kintex-7 325T、410T、420T 与 Virtex-7 485XT、690XT 的设计咨询 — GES 与生产之间的比特流兼容性要求器件：针对 7V690T 生产器件进行了更新 |
| 2012 年 11 月 5 日发布的设计咨询提醒 | |
| (Xilinx 答复 50906) | 生产 Kintex-7 325T、410T 及 Virtex-7 485XT 的更新设计咨询 — GES 与生产器件间的比特流兼容性需求；针对 14.3/2012.3 版本进行了更新 |
| 2012 年 10 月 29 日发布的设计咨询提醒 | |
| (Xilinx 答复 52193) | 7 系列 BPI 多重引导设计咨询 – 当出现回退时，闪存访问总是处于 BPI 异步模式 |
| 2012 年 10 月 22 日发布的设计咨询提醒 | |
| (Xilinx Answer 50617) | 更新了 Kintex-7与 Virtex-7 FPGA 生产 GTX 收发器设计咨询的比特流兼容性部分 |
| 设计咨询提醒（ 2011 年 10 月 17 日） | |
| (Xilinx 答复 44421) | 13.2 iMPACT 的设计咨询 - 错误的间接编程内核文件载入到 Kintex-7 中，导致潜在的设备损坏 |
Artix-7 配置专用设计咨询
| 2016 年 12 月 19 日发布的设计咨询提醒 | |
| (Xilinx 答复 67645) | 有关 7 系列和 UltraScale 架构 FPGA 配置回退和 POST_CRC limitation 限制的设计咨询 |
| 2016 年 10 月 31 日发布的设计咨询提醒: | |
| (Xilinx 答复 68006) | Xilinx 设计工具（Vivado、SDAccel、SDSoC）2016.1 和 2016.2 write_bitstream 的设计咨询 — 多线程可能会导致配置存储器单元设置不正确 |
| 2014 年 11 月 10 日发布的设计咨询提醒 | |
| (Xilinx 答复 62631) | 面向 Vivado 2014.3 的设计咨询 – 针对 7 系列和 Ultrascale FPGA 的编程 eFUSE 寄存器操作失败 |
| 2013 年 8 月 26 日发布的设计咨询提醒： | |
| (Xilinx 答复 57045) | Artix-7/Kintex-7 设计建议 — 在 CFGBVS 设置为 Bank 0 的 VCCO 时，Bank 14 和 15 的配置电压限制为 3.3V 或 2.5V。 |
| 2012 年 10 月 29 日发布的设计咨询提醒 | |
| (Xilinx 答复 52193) | 7 系列 BPI 多重引导设计咨询 – 当出现回退时，闪存访问总是处于 BPI 异步模式 |
较早的架构
如欲查看 6 系列 FPGA 设计咨询的综合列表，请参见下列主答复记录链接
| (Xilinx 答复 34565) | 有关 Virtex-6 FPGA 设计咨询的主要答复记录 |
| (Xilinx 答复 34856) | 有关 Spartan-6 FPGA 设计咨询的主要答复记录 |
Virtex-6 配置专用设计咨询
| 2012 年 8 月 13 日发布的设计咨询提醒: |
|
| (Xilinx Answer 51145) | 设计咨询 - 14.2 iMPACT - 对 Virtex-6 进行间接编程导致工具在无预警的情况下崩溃 |
| 2011 年 8 月 8 日发布的设计咨询提醒: | |
| (Xilinx Answer 42682) | Virtex-6 FPGA 的设计咨询 — 13.x iMPACT — 目标 FPGA 在 JTAG 链中不是唯一器件时，eFUSE 密钥编程错误 |
| 2011 年 7 月 11 日发布的设计咨询提醒: | |
| (Xilinx Answer 41821) | Virtex-6 FPGA 的设计咨询 — BitGen 选项 — g Next_Config_Addr：默认值修改 |
| 2011 年 7 月 6 日发布的设计咨询提醒: | |
| (Xilinx Answer 42682) | Virtex-6 FPGA 的设计咨询 — 13.x iMPACT — 目标 FPGA 在 JTAG 链中不是唯一器件时，eFUSE 密钥编程错误 |
| 2010 年 10 月 18 日发布的设计咨询提醒: | |
| (Xilinx Answer 38134) | Virtex-6 配置 — 在上电没有延迟配置之前，PROGRAM_B 引脚保持为低 |
Spartan-6 配置专用设计咨询
| 2013 年 6 月 19 日发布的设计咨询提醒 |
|
| (Xilinx Answer 56363) | Spartan-6 FPGA 设计咨询 — 如果在配置器件时引脚上出现逆变值，JTAG 边界扫描测试就可能失败。 |
| 2013 年 8 月 2 日发布的设计咨询提醒 | |
| (Xilinx Answer 55037) | Spartan-3A 和 Spartan-6 的设计咨询：在 SelectMAP 配置之后，在启用 Readback CRC 并激发 ABORT 时，Readback CRC 中可能会标记假故障 |
| 2012 年 11 月 19 日发布的设计咨询提醒: | |
| (Xilinx Answer 52716) | 有关 Spartan-6 FPGA 的设计咨询 - 配置读回（如 SEM_IP 或 POST_CRC）会产生配电网络噪声，从而影响 SelectIO 和 GTP 接口 |
| 2011 年 3 月 1 日发布的设计咨询提醒: | |
| (Xilinx Answer 40387) | Spartan-6 配置的设计咨询 — GCLK0 输入可能会在配置末端发生小故障 |
| (Xilinx 答复 40818) | Spartan-6 SelectIO 的设计咨询 — INTERM_XX 在 Spartan-6 FPGA 输入的 BitGen 中没有正确开启 |
| 2010 年 12 月 13 日发布的设计咨询提醒: | |
| (Xilinx Answer 39582) | Spartan-6 的设计咨询 — 使用 POST_CONFIG_CRC 时，INIT_B 引脚不能为用户 I/O |
| 2010 年 11 月 15 日发布的设计咨询提醒: | |
| (Xilinx Answer 38733) | Spartan-6 的设计咨询 — LX100/LX100T SMAP x16 最大 CCLK 频率降低 |