Binary Content Addressable Memory

• Associative array containing arbitrary (key, response) entries.
• Exact match key lookup returns hit/miss result and associated response value on hit.
• High throughput: one lookup per clock cycle up to 600 MHz.
• Flexible, supports a wide range of key widths, response widths and lookup rates with optimized resource utilization.
• Supports all key widths up to 992 bits and all response widths up to 1024 bits.
• Supports both UltraRAM (URAM) and block RAM implementations.
• Scalable, supports one or multiple BCAM instances, each instance can use all block RAM/UltraRAM (URAM) within an SLR allowing very large BCAMs.
• High storage efficiency, 95% of the RAM bits are transformed to CAM bits.
• Supports error correction coding (ECC). Single-bit errors are corrected dynamically during lookups, and permanently with patrol scrubbing.
• Supports Vivado IP integrator.
• Supports entry insert, delete, update using standard TCAM like software APIs.
• Can be inferred from within P4 code using Xilinx® Vitis Networking P4™ tool.

HBM/DDR4 Binary Content Addressable Memory

• Associative array containing arbitrary (key, response) entries.
• Exact match key lookup returns hit/miss result and associated response value on hit.
• High throughput: 150 MLookups/s per HBM/DDR BCAM instance.
• Flexible: Supports a wide range of key widths, response widths, and lookup rates.
• Supports all key widths up to 992 bits and all response widths up to 1013 bits.
• Scalable: Supports one or multiple HBM/DDR BCAM instances, a single instance can use all DRAM within two HBM stacks allowing very large HBM/DDR BCAMs.
• High storage efficiency: 90% of the DRAM bits are transformed to CAM bits.
• Supports Error Correction Coding (ECC) by means of HBM configuration.
• Supports entry insert, delete, and update using highly portable software APIs.
• Can be inferred from within P4 code using the Xilinx Vitis Networking P4 tool.

Semi-Ternary Content Addressable Memory

• Associative array containing arbitrary (key, mask, priority, response) entries.
• Ternary match key lookup returns hit/miss result and associated response value on hit.
• High throughput: one lookup per clock cycle at 600 MHz.
• Flexible: supports a wide range of key widths, response widths and lookup rates with optimized resource utilization.
• Supports all key widths up to 992 bits and all response widths up to 1024 bits.
• Supports both UltraRAM (URAM) and block RAM implementations.
• calable: supports one or multiple STCAM instances, each instance can use all of the block RAM/URAM within an SLR allowing very large STCAMs.
• High storage efficiency, 95% of the RAM bits are transformed to CAM bits.
• Supports error correction coding (ECC). Single-bit errors are corrected dynamically during lookups, and permanently with scrubbing.
• Supports Vivado IP integrator.
• Supports entry insert, delete, update using standard TCAM like software APIs

Ternary Content Addressable Memory

• Associative array containing arbitrary (key, mask, priority, response) entries.
• Ternary match key lookup returns hit/miss result and associated response value on hit.
• High throughput: one lookup per clock cycle at 600 MHz.
• Flexible, supports a wide range of key widths, response widths and lookup rates with optimized resource utilization.
• Supports all key widths up to 991 bits and all response widths up to 1024 bits.
• Up to eight 16-bit wide range comparison fields in each rule minimizes the need for costly rule expansion.
• Supports both UltraRAM (URAM) and block RAM implementations.
• Scalable, supports one or multiple TCAM instances, each instance can use all UltraRAM / block RAM within an SLR allowing for very large TCAMs.
• Supports error correction coding (ECC). Single-bit errors are corrected dynamically during lookups, and permanently with patrol scrubbing.
• Supports Vivado® IP integrator.
• Supports entry insert, delete, update using standard TCAM-like software APIs.
• Can be inferred from within P4 code using Xilinx Vitis Networking P4 tool.