AR# 32147

描述

The ISE Design Suite 11 Release Notes and Licensing Guide found on xilinx.com contains installation instructions, system requirements, and other general information about ISE Design Suite 11.

This Known Issues Answer Record is a supplement to the release notes documentation and contains links to information on known issues in the design tools that might be resolved in future versions.

NOTE: Critical IP Known Issues are captured below in the 11.5 section.General IP Known Issues can be found in IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

解决方案

Other Known Issues Answer Records

(Xilinx Answer 32929) Virtex-6 - 11.x Software Known Issues related to the Virtex-6 FPGA
(Xilinx Answer 32651) Spartan-6 - 11.x Software Known Issues related to the Spartan-6 FPGA
(Xilinx Answer 32288) 11.1 CORE Generator - Known Issues for CORE Generator 11.1 software
(Xilinx Answer 32420) 11.1 ChipScope Pro - Release Notes and Known Issues
(Xilinx Answer 32174) 11.1 System Generator for DSP - Release Notes, README, and Known Issues List
(Xilinx Answer 32176) 11.1 AccelDSP Synthesis Tool - Release Notes, README, and Known Issues List
(Xilinx Answer 32168) 11.1 EDK - EDK Master Answer Record List
(Xilinx Answer 32440) 11.1 iMPACT - Release Notes and Known Issues
(Xilinx Answer 32295) 11.1 ISE - Known Issues for Xilinx software licensing in ISE 11.1
(Xilinx Answer 32492) 11.1 ISE Design Suite Install - Known Issues for ISE Design Suite Install
(Xilinx Answer 33055) 11.2 ISE Design Suite - XilinxUpdate (11.2) Known Issues README
(Xilinx Answer 33381) ISE Design Suite 11 - ISE Simulator (ISim) Known Issues
(Xilinx Answer 32525) 11.1 PlanAhead Known Issues
(Xilinx Answer 32548) 11.1 ISE - Known Issues for Project Navigator 11.1
(Xilinx Answer 32511) 11.1 XST - Known Issues

11.5Known Issues

(SP5)(Xilinx Answer 33849) - Virtex-6 FPGA MMCM - New Requirements for DRP/Phase Shift, VCO minimum frequency, and CLKFBOUT_MULT_F values

(SP5)(Xilinx Answer 33763) - Virtex-6 FPGA Integrated Block Wrapper v1.4, v1.4 rev 1, and v1.4 rev 2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.4 and 11.5

(SP5)(Xilinx Answer 34611) - Virtex-6 FPGA Integrated Block Wrapper v1.4 rev 2 for PCI Express - Patch to Enable VHDL File Generation for v1.4 rev 2 released in ISE 11.5

(SP5)(Xilinx Answer 34612) - Virtex-6 FPGA Integrated Endpoint Block v1.4 for PCI Express - Simulation failure when using ISE 11.5 to simulate a v1.4 core generated in ISE Design Suite 11.4

(SP5)(Xilinx Answer 33277) - Spartan-6 FPGA Integrated Block Wrapper v1.2 and v1.2 rev 1 for PCI Express - Release Notes and Known Issues for ISE Design Suite 11.3, 11.4, and 11.5

(SP5)(Xilinx Answer 34341) Spartan-6 FPGA Integrated Endpoint Block v1.2 for PCI Express - Simulation failure when using ISE 11.5 to simulate a v1.2 core generated in ISE Design Suite 11.3 or 11.4, in 11.5

(SP5)(Xilinx Answer 34451) - Spartan-6 FPGA Integrated Endpoint Block v1.2 rev 1 for PCI Express - Simulation never finishes when simulating a v1.2 rev 1 core generated in ISE Design Suite 11.5

(SP5)(Xilinx Answer 34094) - MIG v3.3, Virtex-6 FPGA DDR2/DDR3 - MMCM CLKFBOUT_MULT_F= 4 not valid, manual modification required

11.4 Known Issues

(SP4)(Xilinx Answer 31788) 11.x ChipScope Pro - "ERROR:MapLib:990 - Map has detected that you are using ChipScope Pro cores generated prior to version 10.1..."

(SP4)(Xilinx Answer 33218) 11.2 - MAP - "FATAL_ERROR:Pack:pksrasliceplanner.c:5683:1.84 - No signal on pin S0 of frag..."

(SP4)(Xilinx Answer 33744) 11.3 Virtex-5 FPGA MAP - Logic corruption related to combination of Global Opt options

(SP4)(Xilinx Answer 33743) 11.3 Virtex-6 FPGA MAP - Change in trimming behavior related to IBUFDS_GTXE1 components

(SP4)(Xilinx Answer 33358) Spartan-6 FPGA MCB - Data Mask cannot be disabled and the UDM and LDM pins cannot be used as General Purpose I/O (GPIO)

(SP4)(Xilinx Answer 33340) 11.2 MAP/PAR - What is meant by Multi-Threading support in ISE 11.2?

(SP4)(Xilinx Answer 32388) 10.1 ChipScope Coregen - ERROR:PhysDesignRules:10 / WARNING:PhysDesignRules:10 - The network <CONTROL<2>> is completely unrouted

(SP4)(Xilinx Answer 32544) Embedded Tri-mode Ethernet MAC Wrapper (Virtex-4) v4.7 - Implementation of MII interface might fail in MAP due to I/O banking rules

(SP4)(Xilinx Answer 33377) MIG v3.2, Virtex-6 FPGA RLDRAMII - Design is unroutable when Debug Signals are turned on

(SP4)(Xilinx Answer 33021) 11.2 Virtex-6 Place - Designs with very low utilization may have very poor QOR

(SP4)(Xilinx Answer 31827) 10.1 MAP - MAP fails with error: "DeleteInterpProc called with active evals" during Phase 10.29

(SP4)(Xilinx Answer 33153) 11.2 Spartan-6 PAR - Incorrect WARNING:ParHelpers:79 message

(SP4)(Xilinx Answer 33783) 11.3 Virtex-5 FPGA Place - Map crashes in placement Phase 9.30 after printing global clock distribution report

(SP4)(Xilinx Answer 32955) 11.2 Timing Analyzer - Clock skew calculations ignores the PRIORITY keyword on the PERIOD constraint

(SP4)(Xilinx Answer 32458) 11.1 Timing Analyzer Release Note - How do you cross-probe to FPGA Editor from Timing Report?

(SP4)(Xilinx Answer 33019) Spartan-6 Clocking - DCM_CLKGEN Spread Spectrum Clock Generation feature support

(SP4)(Xilinx Answer 32457) 11.1 Timing Known Issue - OFFSET IN with FALLING keyword appears to be off by a whole clock cycle

(SP4)(Xilinx Answer 32120) 11.1 Release Notes - PAR/Timing Analyzer/trce - Why do I see Component Switching Limit warnings in my 11.1 PAR report?

(SP4)(Xilinx Answer 32111) 11.1 Known Issue - Timing Analyzer/trce - Advanced Analysis neglects Component Switching Limits

(SP4)(Xilinx Answer 32325) 11.1 Known Issue - Timing Analysis, Virtex-5 - Why does Timing Analyzer fail to issue a Max Period Warning when I use a CRC32 component?

(SP4)(Xilinx Answer 33808) SPI-3 Link Layer v7.1 - Some Spartan-6 designs might fail timing

(SP4)(Xilinx Answer 32445) 11.1 Known Issue - Timing - Incorrect timing analysis associated with input clocks on BUFGMUX

(SP4)(Xilinx Answer 32957) 11.2 Constraint System - Net PERIOD constraints are been pushed from the REFCLK input to the RXRECCLK output of GTP/GTX

(SP4)(Xilinx Answer 32630) 11.1 Constraints - When I use the * wildcard, several of my PINs are missing from my TIMEGRP

(SP4)(Xilinx Answer 30063) 11.1 Known Issue - Constraints Editor/Timing Analyzer - Wrong timing constraint is edited when "Editing Constraints" from Timing Analyzer

(SP4)(Xilinx Answer 32441) 11.1 Known Issue - Timing - Discrete Jitter for PLL/DCM Clock Uncertainty is pessimistic

(SP4)(Xilinx Answer 32505) 11.1 Timing Analyzer - Cross-probing with Timing Analyzer into FPGA Editor is causing warnings

(SP4)(Xilinx Answer 31855) 11.1 Release Note - Timing - Why do I see Component Switching Limit values change in my timing report for PLLs and DCMs?

(SP4)(Xilinx Answer 33007) 11.1 Timing, Virtex-4 - "WARNING:Timing:3327 - Timing Constraint" - Component Switching Limit is limited by DLL portion of the DCM when both DLL and DFS DCM outputs are used

(SP4)(Xilinx Answer 32845) 11.1 Timing Analyzer - The pin name does not match in the Query Nets report and FPGA Editor

(SP4)(Xilinx Answer 32123) 10.1i ISE - Project Navigator fails opening a 10.1i project: "FATAL_ERROR:Portability:PortDynamicLib.c:358:1.29 "

(SP4)(Xilinx Answer 32527) 11.1 ISE - Are Asian characters allowed in the directory path for Project Navigator projects?

(SP4)(Xilinx Answer 32106) 10.1.3 TRCE - I am seeing an extremely large number of paths analyzed in my timing report

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