AR# 58605

2013.3 Vivado IP Release Notes - All IP Change Log Information

描述

This answer record contains all IP change log information from Vivado 2013.3 in a single location which allows you to see IP changes without having to install Vivado Design Suite.

解决方案

32-bit Initiator/Target for PCI (7 series) (5.0)

Version 5.0 (Rev. 2)
Corrected the license key information

3GPP LTE Channel Estimator (2.0)

Version 2.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

3GPP LTE MIMO Decoder (3.0)

Version 3.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

3GPP LTE MIMO Encoder (4.0)

Version 4.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

3GPP Mixed Mode Turbo Decoder (2.0)

Version 2.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

3GPP Turbo Encoder (5.0)

Version 5.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators

3GPPLTE Turbo Encoder (4.0)

Version 4.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

64-bit Initiator/Target for PCI (7 series) (5.0)

Version 5.0 (Rev. 2)
Corrected the license key information

7 Series FPGAs Transceivers Wizard (3.0)

Version 3.0
Updated GTH Attributes and QPLL range - Refer to (Xilinx Answer 56332) and DS183
Updated GTZ Attributes and Clocking
Updated timing constraints (XDC) to resolve Critical Warnings and added support for out-of-context synthesis
Updated timing constraints for recovered clocks in IP level. For details, refer to Migrating section of Product Guide - pg168-gtwizard.pdf
Updated TX and RX FSM to fix MMCM lock synchronization and simulation issues (for all GTs)
GTX TX buffer bypass is enabled in both Manual & Auto modes for single lane as per UG476.
Added check in the GUI to disallow mixed encode/decode for TX and RX
Added GUI option to include or exclude Vivado Lab tools support for debug
Removed LPM and DFE Manual mode option from the GUI
Added checks to limit DRP frequency selection
Protocol templates updated for -- Display port, sRIO gen2, CEI6, Aurora 8B10b
Reduced warnings in synthesis and simulation
Enhanced Support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated clock synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from met stability
Added GUI option to include or exclude shareable logic resources. For details, refer to Upgrading in Vivado Design Suite section of Product Guide - pg168-gtwizard.pdf
Added optional ports to enable transceiver core debug - Refer to pg168-gtwizard.pdf
Updated line rate ranges for A7 Wire bond package from 5.4G to 6.25G
Added support for XC7Z015 and XC7A75T
Moved clock constraints for the recovered clocks to core level xdc file from example design level
Added optional Vivado (ILA and VIO) lab tools support for core debug in example design

7 Series Integrated Block for PCI Express (2.2)

Version 2.2
Reduced Warnings in synthesis and simulation
Implemented Shared Logic for Clocking and Transceiver GT Common blocks to include either in core or example design
Implemented Transceiver Core Debug interface. Brought the debug signals to the port level
Brought the Ext GT DRP signals up to the core top port level
Added support for IPI integrator
Updated XDC to match IP hierarchy
Added support for Cadence IES and Synopsys VCS Simulators
Added support for upgrade from previous versions
Added support for Zynq 7100 device
Added new pages Shared Logic and Core interface Parameters in GUI in Advanced mode
Added Enablement of PCIe DRP interface and made the option true by default
PCIe Sideband interface is broken into several smaller interfaces to connect with DMA IP in IPI
Added support for External PIPE interface mode

AHB-Lite to AXI Bridge (2.1)

Version 2.1 (Rev. 1)
Reduced warnings in synthesis and simulation

AXI 10G-Ethernet (1.0)

Version 1.0
Initial version

AXI AHBLite Bridge (2.1)

Version 2.1 (Rev. 1)
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators

AXI APB Bridge (2.0)

Version 2.0 (Rev. 2)
Reduced warnings in synthesis and simulation

AXI BFM Cores (5.0)

Version 5.0
Param propagation added to AXIS Slave interface
Changed all port names to lower case
Added demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators

AXI BRAM Controller (3.0)

Version 3.0 (Rev. 2)
Updated the port names to lower case
Added example design
Reduced warnings in synthesis and simulation
Improved GUI speed and responsiveness, no functional changes
Added Support for Cadence IES and Synopsys VCS simulators
Changed BRAM Interface DIN and DOUT to match bus interface directions.

AXI CAN (5.0)

Version 5.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Added parameter CS_MTBF_STAGES to specify clock synchronizer stages
Improved GUI speed and responsiveness, no functional changes

AXI Central Direct Memory Access (4.1)

Version 4.1
Enabled cyclic BD feature
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
Improved GUI speed and responsiveness

AXI Chip2Chip Bridge (4.1)

Version 4.1
Added example design
Added demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

AXI Clock Converter (2.1)

Version 2.1
Added parameter SYNCHRONIZATION_STAGES to specify clock synchronizer stages (passed to internal fifo_generator when performing async clock conversion).
Update IP-level XDC with false-path in async clock conversion path.
Eliminate extraneous pipeline registers in aresetn input paths.
Added example design.
Reduced warnings in synthesis and simulation.
Added support for Cadence IES and Synopsys VCS simulators.
Internal FIFO buffers updated to use FIFO Generator v11.0.

AXI Crossbar (2.1)

Version 2.1
Fixed model parameter values for default values of user parameters Mmm_Aaa_BASE_ADDR, Mmm_Aaa_ADDR_WIDTH, Mmm_READ/WRITE_ISSUING.
Changed default Snn_READ/WRITE_ACCEPTANCE = 2, Mmm_READ/WRITE_ISSUING = 4 (for Strategy = Current Settings).
Changed default Mmm_Aaa_ADDR_WIDTH = 0 and Mmm_Aaa_BASE_ADDR = 0xFFFFFFFFFFFFFFFF (unused) for aa > 0.
Fixed Address table display for ADDR_RANGES = 16.
Added validation DRCs for Snn_THREAD_ID_WIDTH, Mmm_Aaa_ADDR_WIDTH and Mmm_Aaa_BASE_ADDR.
Added example design.
Reduced warnings in synthesis and simulation.
Added support for Cadence IES and Synopsys VCS simulators.
Internal FIFO buffers updated to use FIFO Generator v11.0.

AXI Data FIFO (2.1)

Version 2.1
Reduced warnings in synthesis and simulation.
Added support for Cadence IES and Synopsys VCS simulators.
Reduced warnings in synthesis and simulation.
Added support for Cadence IES and Synopsys VCS simulators.
Internal FIFO buffers updated to use FIFO Generator v11.0.

AXI Data Width Converter (2.1)

Version 2.1
Added parameter SYNCHRONIZATION_STAGES to specify clock synchronizer stages (passed to internal fifo_generator when performing async clock conversion).
Fixed RDATA and RRESP value corruption for rare corner cases when upsizing using the FIFO_MODE feature.
Update IP-level XDC with false-path in async clock conversion path.
Eliminate extraneous pipeline registers in aresetn input paths.
Enhanced upsizer single-threading behavior to allow transactions with any ID to propagate without stalling (any FIFO mode setting), reducing overall latency of multi-threaded traffic ~15%.
Added example design.
Reduced warnings in synthesis and simulation.
Added support for Cadence IES and Synopsys VCS simulators.
Internal FIFO buffers updated to use FIFO Generator v11.0.

AXI DataMover (5.1)

Version 5.1
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
Improved GUI speed and responsiveness, no functional changes

AXI Direct Memory Access (7.1)

Version 7.1
Added Micro DMA feature
Added Cyclic BD feature
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
Improved GUI speed and responsiveness

AXI EMC (2.0)

Version 2.0 (Rev. 2)
Updated the functionality to support the multiple banks in sync linear flash mode.
Corrected the functionality for parity bit calculation in Sync SRAM mode.
Support for 7 series devices at Production status
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated to complete transactions for non-existent address regions

AXI EPC (2.0)

Version 2.0 (Rev. 2)
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators

AXI Ethernet (6.0)

Version 6.0
Added option to include or exclude shareable logic resources in the core.
Added support for Board based IO constraints generation.
Enhanced support for IP Integrator.
Added support for upgrade from previous versions.
Updated the address segment name. Please use assign bd address tool command to assign address.
Interface/Port names have changed. Streaming interfaces are now renamed as m_axis_rxd from AXI_STR_RXD and similarly for others. MDIO ports are packaged as an interface. Ports txp txn rxp and rxn are packaged as SGMII or SFP interfaces based on the board connectivity. To reconnect these ports you may use connection automation.

AXI Ethernet Buffer (2.0)

Version 2.0 (Rev. 1)
Updated clock synchronizers to improve Mean Time Between Failures (MTBF) for metastability
Board support package is added
Enhanced support for IP Integrator
Added support for upgrade from previous versions

AXI Ethernet Clocking (2.0)

Version 2.0 (Rev. 1)
Enhanced support for IP Integrator

AXI EthernetLite (2.0)

Version 2.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Support for 7 series devices at Production status
ID WIDTH is added as a user parameter, should be set to '0' for AXILITE Interface

AXI GPIO (2.0)

Version 2.0 (Rev. 2)
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
Improved GUI speed and responsiveness, no functional changes

AXI HWICAP (3.0)

Version 3.0 (Rev. 2)
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
Improved GUI speed and responsiveness, no functional changes

AXI IIC (2.0)

Version 2.0 (Rev. 2)
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
Improved GUI speed and responsiveness, no functional changes

AXI Interconnect (2.1)

Version 2.1
Added support for automatic register slice placement to improve timing.
Increased maximum number of master interfaces to 64 in some configurations.

AXI Interrupt Controller (4.0)

Version 4.0
Hide processor_clk and processor_rst pins when Fast Interrupt is not enabled.
Corrected setting parameters Interrupts Type, Level Type and Edge Type from propagated values.
Fixed XDC critical warning
Support for Automotive Artix-7, Artix-7 Lower Power, Automotive Zynq, Defense Grade Artix-7, Defense Grade Kintex-7, Defense Grade Kintex7 Lower Power, and Defense Grade Zynq devices at Production status
Added synchronization flip-flops on asynchronous interrupt inputs, which adds a two clock cycle latency by default
Changed edge triggered interrupt detection to avoid using the input as clock, which requires that it is active at least one clock cycle

AXI Master Burst (2.0)

Version 2.0 (Rev. 2)
Reduced warnings in synthesis and simulation

AXI Master IPIF (3.0)

Version 3.0 (Rev. 2)
Reduced warnings in synthesis and simulation

AXI Memory Mapped To PCI Express (2.2)

Version 2.2
Added support for shared logic
Usage of PCI_USE_MODE parameter is modified as per gen2 core
Added Out of Context support
Added transceiver Control Debug signals
Added EXT GT DRP signals to core top level
Reduced warnings in synthesis and simulation
Updated XDC to match IP hierarchy
Added support for Cadence IES Simulator
Example design added
Added GES_and_Production for all 7 Series devices.
Added XDC Constraints for clock inputs
Added support for upgrade from previous versions

AXI Memory Mapped to Stream Mapper (1.1)

Version 1.1
Added Product Guide link
Added example design
Reduced warnings in synthesis and simulation

AXI Performance Monitor (5.0)

Version 5.0
Renamed the legacy mode of APM operation as Advanced mode
New modes "Profile" and "Trace" added for high level configuration with fixed 6 counter per slot and more static parameters
Added ID based filtering/Masking, Outstanding transaction support in Advanced mode for Throughput, latency measurement
Additional sampling method support added for non-interrupt based system using memory mapped register read
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

AXI Protocol Checker (1.1)

Version 1.1
Reduced warnings in synthesis and simulation.
Added support for Cadence IES and Synopsys VCS simulators.

AXI Protocol Converter (2.1)

Version 2.1
Reduced warnings in synthesis and simulation.
Added support for Cadence IES and Synopsys VCS simulators.
Internal FIFO buffers updated to use FIFO Generator v11.0.

AXI Quad SPI (3.1)

Version 3.1
Added 32-bit addressing support for eXecute In Place (XIP) mode for Numonyx flash.
In master mode SPISEL port is not enabled and tied to 1 internally
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Resolved the value update issue for C_SCK_RATIO parameter
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

AXI Register Slice (2.1)

Version 2.1
Reduced warnings in synthesis and simulation.
Added support for Cadence IES and Synopsys VCS simulators.

AXI TFT Controller (2.0)

Version 2.0 (Rev. 2)
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

AXI Timebase Watchdog Timer (2.0)

Version 2.0 (Rev. 2)
Fixed parameter propagation of C_WDT_ENABLE_ONCE
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

AXI Timer (2.0)

Version 2.0 (Rev. 2)
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
Improved GUI speed and responsiveness, no functional changes

AXI Traffic Generator (2.0)

Version 2.0
Added Master Loop back mode for AXI4-Stream
Additional TDATA widths supported for AXI4-Stream
Added support for new micro command for processor less system in System Test mode
Added Max test time(in clocks) and Max command retry limit for System Init mode
New external ports Global start/stop added to synchronize all ATGs in a system
Provided initialization support for internal RAMs
High Level Traffic profile mode to generate IP specific AXI traffic-Video, PCIe, Ethernet, USB, Custom(Data)
Added support for upgrade from previous versions
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators

AXI UART16550 (2.0)

Version 2.0 (Rev. 2)
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

AXI USB2 Device (5.0)

Version 5.0
Added support for HSIC PHY
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

AXI Uartlite (2.0)

Version 2.0 (Rev. 2)
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

AXI Video Direct Memory Access (6.1)

Version 6.1
Changed Frame delay default value to 1 in Stride_FrameDly register for genlock slave.
Changed Repeat Enable default value to 0 in DMACR register.
Provided current frame as output on frm_ptr_out in genlock slave mode.
Added new register S2MM_DMA_IRQ_MASK at 0x3C to mask interrupt due to frame or line errors for S2MM channel.
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

AXI Virtual FIFO Controller (2.0)

Version 2.0 (Rev. 2)
Enhanced support for IP Integrator
Reduced warnings in synthesis and simulation
Added example design
Added support for Cadence IES and Synopsys VCS simulators

AXI-Stream FIFO (4.0)

Version 4.0 (Rev. 2)
Selectable transmit and receive path
Enhanced support for IP Integrator
Reduced warnings in synthesis and simulation
Added example design
Added support for Cadence IES and Synopsys VCS simulators

AXI4-Stream Accelerator Adapter (2.0)

Version 2.0
Increased input scalar support to 16
New parameter SCALAR_MODE for each scalar interface supporting AP_NONE, AP_VLD and AP_HS accelerator IO protocol
New ports addition, scalar valid, scalar_ack for input and output scalars
aresetn polarity changed to active low
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Bus Interface updated with all caps

AXI4-Stream Broadcaster (1.1)

Version 1.1
Added example design
Improved support for multiple instances

AXI4-Stream Clock Converter (1.1)

Version 1.1
Fixed bug of incorrect clock ratios set in verilog wrapper when using any synchronous ratio other than 1:2.
Updated to FIFO Generator v11.0
Added example design
Updated Clock crossing constraints to match FIFO Generator.
Updated clock synchronizers to improve Mean Time Between Failures (MTBF) for metastability. Added parameter SYNCHRONIZATION_STAGE to specify clock synchronizer stages.
Reduced warnings in synthesis and simulation

AXI4-Stream Combiner (1.1)

Version 1.1
Added example design

AXI4-Stream Data FIFO (1.1)

Version 1.1
Updated to FIFO Generator v11.0
Added example design
Updated Clock crossing constraints to match FIFO Generator.
Updated clock synchronizers to improve Mean Time Between Failures (MTBF) for metastability. Added parameter SYNCHRONIZATION_STAGE to specify clock synchronizer stages.

AXI4-Stream Data Width Converter (1.1)

Version 1.1
Added example design
Initial default value for maximum range of TUSER bits per num TDATA bytes changed from 32 to 2048 to correspond with a TDATA number of bytes of 2. Absolute TUSER width limit is 4096 bits wide.
Reduced warnings in synthesis and simulation

AXI4-Stream Interconnect (2.1)

Version 2.1
Added parameters SYNCHRONIZATION_STAGES, ENABLE_ADVANCED_OPTIONS, ENABLE_FIFO_COUNT_PORTS; existing IP instances unchanged
Added optional port Snn_ARB_REQ_SUPPRESS, present if NUM_SI > 1 and NUM_MI ==1 and ARB_ALGORITHM != 2
Added optional port Snn_AXIS_DATA_COUNT, Snn_AXIS_RD_DATA_COUNT, Snn_AXIS_WR_DATA_COUNT, present when ENABLE_FIFO_COUNT_PORTS == 1 and Snn_FIFO_DEPTH > 0
Added optional port Mmm_AXIS_DATA_COUNT, Mmm_AXIS_RD_DATA_COUNT, Mmm_AXIS_WR_DATA_COUNT, present when ENABLE_FIFO_COUNT_PORTS == 1 and Mmm_FIFO_DEPTH > 0
Ease-of-use enhancements.

AXI4-Stream Protocol Checker (1.1)

Version 1.1
Added example design

AXI4-Stream Register Slice (1.1)

Version 1.1
Added example design
Reduced warnings in synthesis and simulation

AXI4-Stream Subset Converter (1.1)

Version 1.1
Added example design
GUI parameter 'Generate TLAST' only enabled when SI TLAST disabled and MI TLAST enabled.
Improved support for multiple instances

AXI4-Stream Switch (1.1)

Version 1.1
Port s_req_suppress is optional, present when NUM_SI > 1 and NUM_MI == 1
Added example design
Reduced warnings in synthesis

AXI4-Stream to Video Out (3.0)

Version 3.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for Cadence IES and Synopsys VCS simulators

Accumulator (12.0)

Version 12.0 (Rev. 2)
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators

Adder Subtracter (12.0)

Version 12.0 (Rev. 2)
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators

Asynchronous Sample Rate Converter (2.0)

Version 2.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators

Aurora 64B66B (9.0)

Version 9.0
Provided Verilog source and VHDL netlist
TX startup state machine update for MMCM lock synchronization with stable clock
Rx startup state machine updates to handle the RxReset after valid data is received
Linear 32-bit datapath interface from GT RX
Lane skew tolerance enhancement, now able to tolerate more lane to lane skew
Polarity inversion logic is enabled
Common reset and controls across all lanes
Increased the Rx CDR lock time from 50KUI to 37MUI as suggested by GT user guide
Increased the Block sync header max count from 64 to 60K to increase the robustness of the link
Transmission of more idle characters to add more robustness to link
Channel_INIT state machine and TX startup state machine are updated for hotplug sequence
Removed the reset to scrambler and made it free running to achieve faster CDR lock
Fixed corner case packet drop during CC( Clock Correction) insertion
Updated GTH QPLL attributes - Refer to (Xilinx Answer 56332)
Ease Of Use Updates. For details, refer to migrating and upgrading section of Product Guide
Added GUI option to include or exclude shareable logic resources in the core
Added optional transceiver control and status ports
Updated synchronizers for clock domain crossing to reduce "Mean Time Between Failures" (MTBF) from meta-stability
Reduced warnings in synthesis and simulation
Added support for Cadence IES and Synopsys VCS simulators
Basic Support for IP Integrator
XDC constraints updated to constrain 1st stage of the synchronizer flop
Added GUI option to include or exclude Vivado Labtools support for debug
Added quality counters in example design to increase the test quality
Added hardware reset state machine in example design to perform repeat reset testing

Aurora 8B10B (10.0)

Version 10.0
Added support for XC7A75T device
Added startup FSM integration for 7 series GT reset sequence
Added GUI option to include or exclude Vivado Labtools support for debug
Updated line rate for A7 wire bond package devices for speed grade -2 and -3
Added GUI option to include or exclude shareable logic resources in the core. For details, refer to Migrating section of Product Guide - pg046-aurora-8b10b.pdf
Added optional transceiver control and status ports - Refer to pg046-aurora-8b10b.pdf
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
Reduced warnings in synthesis and simulation
Added support for Cadence IES and Synopsys VCS simulators
Added support for IP Integrator level 0

Binary Counter (12.0)

Version 12.0 (Rev. 2)
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators

Block Memory Generator (8.0)

Version 8.0 (Rev. 2)
The previous version of BLK MEM GEN was not displaying the power estimation numbers in the XGUI. This issue got fixed in this revision
Implemented additional checks in GUI, improved speed and responsive of GUI
Reduced synthesis and simulation warnings
Added support for Cadence IES and Synopsys VCS simulators
Unused Address bits of the primitive are tied to '1' as per the 7 series user guide.
Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN"
Fixed collision warning issue in VHDL behavioral model
GUI logic modified to preserve the Depth field as long as the value falls in the valid range even after change in the WIDTH
Changed "RDADDR_COLLISION_HWCONFIG" attribute to "Performance" for Single-port BRAM configurations for primitive widths lesser than 36 for RAMB18E1 and 72 for RAMB36E1.
FIxed the BRAM initialization issue for Simple Dual Port configuration for cascade modes with depth >32K

CIC Compiler (4.0)

Version 4.0 (Rev. 2)
Updated USE_MULT attribute on DSP48 slices to "NONE" to save power
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Fixed GUI parameter out of range error for maximum rate value when rate is programmable, no change in functionality
Added support for Cadence IES and Synopsys VCS simulators

CORDIC (6.0)

Version 6.0 (Rev. 2)
Addition of C model
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008
C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll

CPRI (8.0)

Version 8.0
Option to bypass Ethernet frame buffers added.
In 9.8380Gbps capable cores the unused PLL is now powered down.
Added support for IP Integrator.
Added support for out of context flow.
Reduced warnings in synthesis.
Reduced warnings in simulation.
Added support for Cadence IES and Synopsys VCS simulators.
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability.
Added GUI option to include or exclude shareable logic resources in the core.
Added optional transceiver control and status ports.

Chroma Resampler (4.0)

Version 4.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Clocking Wizard (5.1)

Version 5.1
Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL
Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
Fixed precision issues between displayed and actual frequencies
Added tool tips to GUI
Added Jitter and Phase error values to IP properties
Added support for Cadence IES and Synopsys VCS simulators
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator

Color Correction Matrix (6.0)

Version 6.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Color Filter Array Interpolation (7.0)

Version 7.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Complex Multiplier (6.0)

Version 6.0 (Rev. 2)
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Optimized support for UltraScale devices
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008
C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll

Convolution Encoder (9.0)

Version 9.0 (Rev. 2)
Fixed demonstration testbench to avoid division by zero error when simulating with VCS
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators

DDS Compiler (6.0)

Version 6.0 (Rev. 2)
Cosmetic GUI changes to table header row, no change in functionality
Fixed issue where the behavior of 2-channel rasterized configurations produced incorrect outputs.
See (Xilinx Answer 56597).
Fixed issue of incorrect sign extension of M_AXIS_PHASE_TDATA for Rasterized configurations.
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Fixed issue of C model crash when calling reset function with configurations without a phase generator.
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

DSP48 Macro (3.0)

Version 3.0 (Rev. 2)
Cosmetic GUI changes to table header row, no change in functionality
Internal standardization in source file delivery, does not change behavior
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Optimized support for UltraScale devices

DUC/DDC Compiler (3.0)

Version 3.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Defective Pixel Correction (7.0)

Version 7.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Discrete Fourier Transform (4.0)

Version 4.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

DisplayPort (4.1)

Version 4.1
Reduced warnings in Synthesis and Simulation
Added GUI option to include or exclude shareable logic resources in the core, for more information on this change please refer to the Migrating section in the Product Guide
Added optional transceiver control and status ports
Added support for Zynq devices
Updated clock synchronizers to improve Mean Time Between Failures (MTBF) for metastability
Added GUI option to select Bi-directional / Uni-directional IOs for AUX
Upgraded the fifo_generator_v10_0 to fifo_generator_v11_0
MST Transmit Interop Related Updates
Added optional ports (MST related), existing IP instances are unchanged
Added output pixel mode and hres/vres ports for sink controller
AUX Filter and IIC 1-sec timeout updates
XDC File Updates for cross-clock paths
Enhanced support for IP Integrator

Distributed Memory Generator (8.0)

Version 8.0 (Rev. 2)
Enhanced support for IP Integrator
Reduced warnings in synthesis and simulation
Added support for Cadence IES and Synopsys VCS simulators

Divider Generator (5.1)

Version 5.1
Addition of LUT-Mult architecture
Addition of configurable latency to Radix 2 architecture
Addition of C model
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added support for Cadence IES and Synopsys VCS simulators
Added default constraints for out of context flow
Added support for IP Integrator
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008
C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll

ECC (2.0)

Version 2.0 (Rev. 2)
Added example design
Added demonstration testbench
Reduced warnings in synthesis and simulation
Added support for Cadence IES and Synopsys VCS simulators

Ethernet 1000BASE-X PCS/PMA or SGMII (14.0)

Version 14.0
Link timer value ports removed from block_wrapper
GT updates for Series-7 transceivers (Termination settings updates, attribute updates, hierarchy update).
Enhanced support for IP Integrator.
Reduced warnings in synthesis and simulation.
Updated clock synchronizers to improve Mean Time Between Failures (MTBF) for metastability.
Added optional transceiver control and status ports.
Added support for the out of context flow.
Added GUI option to include or exclude shareable logic resources in the core. Please refer to the Product Guide for information and port changes.
New board GUI tab for targeting evaluation boards
Marking Production for Virtex-7 and Zynq-7000 families.

Ethernet PHY MII to Reduced MII (2.0)

Version 2.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator

FIFO Generator (11.0)

Version 11.0
AXI ID Tags (s_axi_wid and m_axi_wid) are now determined by AXI protocol type (AXI4, AXI3). When upgrading from previously released core, these signals will be removed when AXI_Type = AXI4_Full.
AXI Lock signals (s_axi_awlock, m_axi_awlock, s_axi_arlock and m_axi_arlock) are now determined by AXI Protocol type (AXI4, AXI3). When upgrading from previously released core, these signals width will reduce from 2-bits to 1-bit when AXI_Type=AXI4_Full
Removed restriction on packet size in AXI4 Stream FIFO mode. Now, the packet size can be up to FIFO depth
Enhanced support for IP Integrator
Reduced warnings in synthesis and simulation
Added support for Cadence IES and Synopsys VCS simulators
Improved GUI speed and responsiveness, no functional changes
Increased the maximum number of synchronization stages from 4 to 8. The minimum FIFO depth is limited to 32 when number of synchronization stages is > 4

FIR Compiler (7.1)

Version 7.1 (Rev. 1)
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Optimized support for UltraScale devices
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008
C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll

Fast Fourier Transform (9.0)

Version 9.0 (Rev. 2)
Cosmetic GUI changes to table header row, no change in functionality
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Optimized support for UltraScale devices
Fixed demonstration testbench elaboration errors - see (Xilinx Answer 56322).
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Fixed Interval Timer (2.0)

Version 2.0 (Rev. 2)
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Kintex-7 Lower Power, and Defense Grade Zynq devices at Production status

Floating-point (7.0)

Version 7.0 (Rev. 2)
Warning. For the Floating Point Accumulator configured with C_MULT_USE = full_usage, output values from any post-synthesis model may be incorrect. The behavioral model outputs will be correct. Recommend use C_MULT_USE = medium_usage. This will be fixed in 2013.4. CR739694
Cosmetic GUI changes to table header row, no change in functionality
Added additional support for future devices
Behavioral VHDL model replaced by Encrypted RTL
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix7, Automotive Zynq, Defense Grade Artix7 Defense Grade Zynq and Lower Power Artix7 devices at Production Status
Added support for Cadence IES and Synopsys VCS simulators
Added default constraints for out of context flow
Added support for IP Integrator
Optimized support for UltraScale devices
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008
C model updated to use third-party library MPIR version 2.6.0 (previously was version 2.2.1); the Windows MPIR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll
C model updated to use third-party library MPFR version 3.1.2 (previously was version 3.0.1); the Windows MPFR DLLs are also statically linked to the Windows CRT library, to remove the dependency on MSVCRT90.dll

G.709 FEC Encoder/Decoder (2.0)

Version 2.0 (Rev. 2)
Beta support for future devices
Support for glitch handling
Addition of reference design and testbench to Vivado
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix7, Automotive Zynq, Defense Grade Artix7 Defense Grade Zynq and Lower Power Artix7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

Version 1.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

Version 2.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Optimizations to improve GUI startup speed
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Fixed demo testbench to use package from work

Gamma Correction (7.0)

Version 7.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Visual GUI enhancements - no change to functionality
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Gmii to Rgmii (3.0)

Version 3.0
Added bus interface definitions.
Changed data type of GUI option PHY Address to integer form binary.
Added GUI option to provide 2ns skew on RGMII TXC.
Added GUI option to include or exclude IDELAYCTRL instantiation.
Added GUI option to include or exclude shareable logic resources in the core.
Enhanced support for IP Integrator.
Reduced warnings in synthesis and simulation.
Updated clock synchronizers to improve Mean Time Between Failures (MTBF) for metastability.

IBERT 7 Series GTH (3.0)

Version 3.0 (Rev. 2)
When Quad 217 is selected in an IBERT design, the reference clock source was not properly connected to GT which caused a placer failure. This issue is fixed.
Added support to forward clock interchangeably. This means Quad A can forward clock to Quad B and Quad B can forward clock to Quad A. Both quad A & B are operating on forwarded clocks.
Added support to forward clock from non-selected quad.

IBERT 7 Series GTP (3.0)

Version 3.0 (Rev. 2)
Fixed IP customization issue

IBERT 7 Series GTX (3.0)

Version 3.0 (Rev. 2)
Added new device support for xc7z030fbg484.

IBERT 7 Series GTZ (3.1)

Version 3.1
TXUSERCLK_SEL_LANEx and RXUSRCLK_SEL_LANEx are modified for South octal to reflect polarity change. This will remove the usage of tcl file while bringing up the South Octal GTZ design on hardware in runtime tools. This necessitates a Minor version update to the core.
If Lane0 is in Power Down mode, the links of other lanes in that Octal wont be up on hardware. So the Power Down option for Lane0 in an Octal is disabled.
Resolved the issue of showing 2 IBERT consoles in Serial I/O Analyzer when 2 octal design is selected. Now only 1 IBERT console is seen even when 2 octals are selected.

ILA (Integrated Logic Analyzer) (3.0)

Version 3.0
All ports changed to lower case
Added ILA Advanced Trigger Features

IOModule (2.1)

Version 2.1
Added support for board level constraints
Corrected setting of parameters C_INTC_LEVEL_EDGE and C_INTC_POSITIVE from propagated values
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, and Defense Grade Zynq devices at Production status

Image Characterization (3.00.a)

Version 3.00.a
No changes

Image Enhancement (8.0)

Version 8.0 (Rev. 1)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Image Noise Reduction (6.0)

Version 6.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Image Statistics (6.0)

Version 6.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Interleaver/De-interleaver (8.0)

Version 8.0 (Rev. 2)
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added support for Cadence IES and Synopsys VCS simulators
Added default constraints for out of context flow

JESD204 (5.0)

Version 5.0
Added GUI option to include or exclude RPAT and JSPAT modules.
Removed GUI option to generate shared core. Use Shared Logic Tab to control GT sharing in this version.
Removed GUI option for JESD204 Subclass selection. Subclass is now selected using a register.
IPIF has been updated to latest version (v2.0).
AXI4-Lite Address map has been updated.
Count Error module now calculates all byte errors in received data.
A single AXI Streaming bus is used for all txdata and rxdata lanes.
The Hardware Demo design is no longer provided with the core and is only available as a separate download.
The maximum multiframe size is now limited to 1000 octets.
Pins added to select between CPLL and QPLL in GTX and GTH devices.
Added GTX watchdog timer logic in Zynq devices. The watchdog timer was only generated for Virtex and Kintex devices prior to this revision.
Fix error reporting by SYNC interface. rx_tvalid incorrectly de-asserted when errors were reported using SYNC~
Fix loss of sync and error reporting using sync interface to be fully compliant with JESD204B specification.
Fix for subclass 1 periodic SYSREF where SYSREF was not reliably captured unless it was a single cycle pulse.
sysref_always behavior changed to force SYNC~ assertion if the position of SYSREF changes when sysref_always=1.
GTX and GTH now default to 4 byte alignment and GTP to 2 byte alignment to ensure received AXI data is word aligned.
Added support for IP Integrator.
Added support for out of context flow.
Reduced warnings in synthesis and simulation.
Added support for Cadence IES and Synopsys VCS simulators.
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability.
Added GUI option to include or exclude shareable logic resources in the core.
Added optional transceiver control and status ports.

JTAG to AXI Master (1.0)

Version 1.0
Native Vivado Release

LMB BRAM Controller (4.0)

Version 4.0 (Rev. 2)
Added MASTER_TYPE property on the BRAM interface
Changed BRAM interface DIN and DOUT to match bus interface directions
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, and Defense Grade Zynq devices at Production status
Ensure that other masters are excluded from C_MASK calculation

LTE DL Channel Encoder (3.0)

Version 3.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

LTE Fast Fourier Transform (2.0)

Version 2.0 (Rev. 2)
Cosmetic GUI changes to table header row, no change in functionality
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

LTE PUCCH Receiver (2.0)

Version 2.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

LTE RACH Detector (2.0)

Version 2.0 (Rev. 2)
Cosmetic GUI change to parameter order - no change to functionality
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
RTL updates for simulator support, no change in functionality
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

LTE UL Channel Decoder (4.0)

Version 4.0 (Rev. 2)
Removed dependency on XilinxCoreLib from demonstration testbench
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Linear Algebra Toolkit (2.0)

Version 2.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Cosmetic GUI changes to table header row, no change in functionality
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Local Memory Bus (LMB) 1.0 (3.0)

Version 3.0 (Rev. 2)
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, and Defense Grade Zynq devices at Production status

Mailbox (2.0)

Version 2.0 (Rev. 2)
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, and Defense Grade Zynq devices at Production status

Memory Interface Generator (MIG 7 Series) (2.0)

Version 2.0 (Rev. 1)
Added support for ILA 3.0 and VIO 3.0
Resolved controller hang issues on read-modify-write commands (See (Xilinx Answer 54710))
Resolved Clock Driver Enable settings for RC1 on RDIMM interfaces (See (Xilinx Answer 57279))
Updated Chipscope debug signals for OCLKDELAY calibration (See Xilinx Answer 54918)
Resolved timing failures with larger SSI devices (See (Xilinx Answer 56385))
Added AXI addressing support over 32 bits for DDR2 and DDR3
Corrected Chip Select width for single rank RDIMM devices (See (Xilinx Answer 57436))

MicroBlaze (9.2)

Version 9.2
Vivado-only core, with no functional changes compared to EDK version 8.50.c
Fixed issues causing an Instruction Bus Exception on a branch instruction to be handled incorrectly. Versions that have this issue: 9.1, 9.0, 8.40.b, 8.40.a, 8.30.a, 8.20.b, 8.20.a, 8.10.d, 8.10.c, 8.10.b, 8.10.a, 8.00.b, 8.00.a, 7.30.b, 7.30.a, 7.20.d, 7.20.c, 7.20.b, 7.20.a, 7.10.d, 7.10.c, 7.10.b, 7.10.a, 7.00.b, 7.00.a. Can only occur when area optimization is enabled, and either instruction bus exception or fault tolerance is enabled.
Avoid rare issue that can cause loss of coherency. Versions that have this issue: 8.50.b, 8.50.a. Can only occur when coherency is enabled by setting C_INTERCONNECT = 3.
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, and Defense Grade Zynq devices at Production status
Reduced warnings in synthesis and simulation

MicroBlaze Debug Module (MDM) (3.0)

Version 3.0 (Rev. 2)
Reduced warnings in simulation
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, and Defense Grade Zynq devices at Production status

MicroBlaze MCS (2.0)

Version 2.0 (Rev. 2)
Added support for board level constraints
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, and Defense Grade Zynq devices at Production status

Motion Adaptive Noise Reduction (6.0)

Version 6.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Multiplier (12.0)

Version 12.0 (Rev. 2)
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Optimized support for UltraScale devices

Multiply Accumulator (3.0)

Version 3.0 (Rev. 2)
Fixed behavior for MACC Extend configuration which did not match hardware behavior
Internal standardization in source file delivery, does not change behavior
Behavioral VHDL model replaced by Encrypted RTL
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators

Multiply Adder (3.0)

Version 3.0 (Rev. 2)
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators

Mutex (2.0)

Version 2.0 (Rev. 2)
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, and Defense Grade Zynq devices at Production status

Object Segmentation (3.00.a)

Version 3.00.a (Rev. 2)
Added support for Synopsys VCS simulator (post-synthesis or post-implementation Verilog simulation flows only)

Peak Cancellation Crest Factor Reduction (4.0)

Version 4.0 (Rev. 2)
Cosmetic GUI changes to table header row, no change in functionality
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Proc Sys Reset (5.0)

Version 5.0 (Rev. 2)
Changed board flow specific parameter name as per new requirements
Added example design and demonstration testbench
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
Support for 7 series devices at Production status

QSGMII (3.0)

Version 3.0
Removed static MDIO PHY Address ports and make programmable while generation through GUI
Removed Link Timer ports and tied to 1.64 ms for synthesis and 0.14 ms for simulation
GT updates for Series-7 transceivers (Termination settings updates, attribute updates, hierarchy update).
Enhanced support for IP Integrator.
Reduced warnings in synthesis and simulation.
Updated clock synchronizers to improve Mean Time Between Failures (MTBF) for metastability.
Added support for the out of context flow.
Added GUI option to include or exclude shareable logic resources in the core. Please refer to the Product Guide for information and port changes.
Added GUI option to include or exclude configuration vector ports
Added optional transceiver control and status ports.

RAM-based Shift Register (12.0)

Version 12.0 (Rev. 2)
Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators

RGB to YCrCb Color-Space Converter (7.1)

Version 7.1
Added auto upgrade support from previous version.
The GUI (Features - Converter Type - Input Range Selection) has been changed to Output Range Selection
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

RXAUI (4.0)

Version 4.0
Moved Artix-7 and Zynq-7000 devices to production
FBG packages enabled
Fixed 7 series GTP reset logic (Xilinx Answer 56313)
Added support for IP Integrator.
Updated synchronizers to improve Mean Time Between Failures (MTBF) for metastability.
GUI 'Shared Logic' section revised to make the options clearer
The HDL parameter WRAPPER_SIM_GTRESET_SPEEDUP has been removed. To control the GT simulation parameter refer to the Product Guide.
clk156 is now always a core output (clk156_out) driven by a BUFH. This clock cannot be shared with other RXAUI core instances due to the GT buffer bypass mechanism.
The gt_control port has been removed and the debug port width changed to just contain RXAUI information. To enable the transceiver control ports recustomize and enable 'additional transceiver ports'
DRP ports are now only present if the additional transceiver control ports are enabled
Top level ports changed to make connecting a core with shared logic to a core without shared logic easier
Example Design changed to include a synthesizable pattern generator and checker.
Clock buffer changed from a BUFG to BUFH. To revert this back to a BUFG please see (Xilinx Answer 57546)
Path to the transceivers has changed. This is now of the form /gt0_gt_wrapper_i/gtxe2_i. This will affect constraints if you use the X0Y1 style of naming. (Pin package constraints unchanged)
Updated 7 Series Transceiver Attributes (including (Xilinx Answer 56332))
QPLL for GTH transceivers is now powered down by default (unused)
Fixed VHDL chbond_counter logic - core could fail to issue a reset if all lanes achieved sync

Reed-Solomon Decoder (9.0)

Version 9.0 (Rev. 2)
Repackaged for internal optimizations, no functional changes
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators

Reed-Solomon Encoder (9.0)

Version 9.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators

S/PDIF (2.0)

Version 2.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator
Added support for Cadence IES and Synopsys VCS simulators
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

SDI RX to Video Bridge (1.0)

Version 1.0
Initial release

SMPTE 2022-1/2 Video over IP Receiver (1.0)

Version 1.0
Native Vivado Release

SMPTE 2022-1/2 Video over IP Transmitter (1.0)

Version 1.0
Initial release

SMPTE SD/HD/3G-SDI (3.0)

Version 3.0
Updated to change the port name from mixed case to lower case
Reduced warnings in synthesis and simulation
Added support for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Added support for Demo Testbench

SMPTE2022-5/6 Video over IP Receiver (3.0)

Version 3.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context

SMPTE2022-5/6 Video over IP Transmitter (3.0)

Version 3.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context

SPI-4.2 (13.0)

Version 13.0 (Rev. 2)
Added support for Cadence IES and Synopsys VCS simulators
Updated clock synchronizers to improve Mean Time Between Failures (MTBF) for metastability.
Support for Virtex-7 devices at Production status

SelectIO Interface Wizard (5.1)

Version 5.1
Added ability to use Clock Enable port of ISERDES or OSERDES
Added GUI option to configure clock type and IO standard for forwarded clock port
Added tool tips to GUI
Added support for Cadence IES and Synopsys VCS simulators
Reduced warnings in synthesis and simulation
Added support for IP Integrator

Serial RapidIO Gen2 (3.0)

Version 3.0
Added support for Cadence IES and Synopsys VCS simulators
Added optional transceiver control and status ports
Changed core boundary to include all required logic
Added GUI option to include or exclude shareable logic resources in the core
Enhanced support for IP Integrator
ISE specific meta-data support is removed

Soft Error Mitigation (4.0)

Version 4.0 (Rev. 2)
Increased pblock dimensions in the example design constraint file for Virtex-7 devices to fully contain logic. These pblocks may be manually reduced when integrating the IP into a larger design. Improved packing may reduce the design FIT. (AR47338)
Moved pblock closer to the ICAP in the example design constraint file for 7z100 devices to improve timing.
Added support for Cadence IES and Synopsys VCS simulators.
Added support for xc7a75t, xc7a75tl, and xc7z015 devices.
Support for xc7a75t, xc7a75tl, xc7z015, and xc7vh870t devices at Pre-Production status. All other supported devices at Production status.

System Cache (3.0)

Version 3.0 (Rev. 2)
Fixed issue where some control register access with cache coherent configuration could hang
Fixed issue where cache line in rare circumstances could be unusable if rest occurs during allocation of that line
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, and Defense Grade Zynq devices at Production status

Ten Gigabit Ethernet MAC (13.0)

Version 13.0
Supported Artix-7 parts moved to production.
XDC now delivered with simulation-only license.
Replaced MMCM_BASE primitives with 7 series native MMCM2_BASE primitives.
Added a default case to next state decoding in AXI-Lite slave attachment block.
Use inferred rather than instanced block RAM in the FIFO in the example design.
Change parameters to upper case in example design FIFO files.
Remove BUFG from feedback path in transmit MMCM
Added GUI option to include or exclude shareable logic resources in the core. Please refer to the Product Guide for information and port changes.
Added missing -datapath_only switch to some clock-crossing paths inside the core.
Added missing begin/end to Verilog example design address swap block
Removed the C_BASE_ADDRESS RTL parameter and shrunk AXI4-Lite address bus from 32 bits to 10 bits; address decoding for upper bits is done in AXI-Interconnect core now.
Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability.
Added support for Cadence IES and Synopsys VCS simulators.
Added support for IP Integrator.

Ten Gigabit Ethernet PCS/PMA (10GBASE-R/KR) (4.0)

Version 4.0
Virtex-7, Kintex-7 and Zynq-7000 now support at Production status
Added GUI option to include or exclude shareable logic resources in the core. Port changes on core.
Added optional transceiver control and status ports.
New ports added to allow user access to transceiver DRP ports.
All port changes are documented in the core Product Guide.
PCS Block Lock FSM rewritten to remove the corner-case failure in UNH test 49.3.3
AutoNegotiation RX block fixed for Consistency Match issue: C.M. was not detected if first 3 identical frames received all had Ack set. Very unlikely to occur in real-world application.
Main core reset now also resets all PMA registers to defaults
Revised requirement for DCLK to be 1/2 rate of clk156. DCLK now has to be driven directly by clk156.
Updated 7 Series GTH QPLL attributes (see (Xilinx Answer 56332))
Added support for the out of context flow.

Test Pattern Generator (5.0)

Version 5.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Added Bayer sub-sampling

Timer Sync 1588 (1.1)

Version 1.1 (Rev. 1)
Simplified the core customization GUI
Enhanced support for IP Integrator
Reduced warnings in synthesis and simulation
Added support for out of context flow

Tri Mode Ethernet MAC (8.0)

Version 8.0
Added Pre-Production support for 7 series Automotive and Defense-grade parts.
Added GUI option to include or exclude shareable logic resources in the core. Please refer to the Product Guide for information and port changes.
The MII now uses regional (BUFR) clock buffers instead of global (BUFG).
The GUI now defaults to the full duplex only option rather than full and half duplex support.
The IDELAYCTRL RDY signal has been included in the IDELAYCTRL RST generation logic.
Use inferred rather than instanced block RAM in the FIFO of the example design.
The transmit FIFO of the example design has been enhanced to drop very short undersized frames. This protects against a potential address mis alignment condition. Please refer to (Xilinx Answer 56267).
Added support for the out of context flow.
Added support for Cadence IES simulator.
Added support for Synopsys VCS simulator (post synthesis or post implementation Verilog simulation flows only).
Reduced warnings in synthesis and simulation.
Shortened directory and file names of source files to help reduce overall path length.
When a Vivado project is targeted at either the KC705 of AC701 evaulation boards, a new Board GUI tab will appear to allow the user to connect the core to the on-board Ethernet PHY.
Updated the XDC constraints appropriately for any applicable version 8.0 change and to match the latest recommendations.
Enhanced support for IP Integrator by including additional bus I/F definitions and clock frequency metadata.
For IP Integrator, previous bus I/F names have been renamed for consistency. Upgraded IP Integrator designs using this core will require reconnection of the Bus I/F's.

VIO (Virtual Input/Output) (3.0)

Version 3.0
Port Names changed to lower case

Video Deinterlacer (4.0)

Version 4.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Video In to AXI4-Stream (3.0)

Version 3.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for Cadence IES and Synopsys VCS simulators
Added support for out of context flow

Video On Screen Display (6.0)

Version 6.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Added support for Cadence IES and Synopsys VCS simulators
Updated GUI Layout and parameter allowable ranges
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Video Scaler (8.1)

Version 8.1 (Rev. 1)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

Video Timing Controller (6.0)

Version 6.0 (Rev. 2)
Reduced warnings in synthesis and simulation
Added support for out of context flow
Added support for Cadence IES and Synopsys VCS simulators

Video to SDI TX Bridge (1.0)

Version 1.0
Initial release

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (2.2)

Version 2.2
Reduced warnings in synthesis and simulation
Implemented Shared Logic for Clocking and Transceiver GT Common blocks to include either in core or example design
Implemented Transceiver Core Debug interface. Brought the debug signals to the port level
Brought the Ext GT DRP signals up to the core top port level
Added support for IPI integrator
Updated XDC to match IP hierarchy
Added support for Cadence IES and Synopsys VCS Simulators
Added support for upgrading the core from previous versions
Added new pages Shared Logic and Core interface Parameters in GUI in Advanced mode
Brought PCIE DRP Ports up to the core top and enabled depending on PCIE_DRP parameter (Advanced mode)
PCIe Sideband interface is broken into several smaller interfaces to connect with DMA IP in IPI

Viterbi Decoder (9.0)

Version 9.0 (Rev. 2)
Internal standardization in source file delivery, does not change behavior
Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status
Added default constraints for out of context flow
Added support for Cadence IES and Synopsys VCS simulators

XADC Wizard (3.0)

Version 3.0 (Rev. 2)
Updated AXI4 Streaming FIFO depth from [1:1017] to [7:1020]
Added check to disable invalid Vauxp/Vauxn pairs for x*7z010clg225 Zynq device
Defined Vp/Vn and Vauxp/Vauxn as bus interfaces, no functional change
Added option in GUI to provide relative path for sim file, no functional change
Added a summary tab in the GUI, no functional change
Added support for Cadence IES and Synopsys VCS simulators
Reduced warnings in synthesis and simulation
Enhanced support for IP Integrator

XAUI (12.0)

Version 12.0
Artix-7 and Zynq-7000 devices now supported at Production status
FBG packages enabled
Added support for upgrade from previous versions.
Added optional transceiver control and status ports support.
Added support for IP Integrator.
Fixed 7 Series GTP/GTH reset logic (see (Xilinx Answer 56312)).
Updated synchronizers to improve Mean Time Between Failures (MTBF) for metastability.
clk156 is now always a core output (clk156_out) driven by a BUFG. This clock cannot be shared with other XAUI core instances due to the GT buffer bypass mechanism.
DRP ports are now only present if the additional transceiver control ports are enabled
Added support for the out of context flow.
Added GUI option to include or exclude shareable logic resources in the core. Please refer to the Product Guide for information and port changes.
Updated 7 Series GTH QPLL attributes; see (Xilinx Answer 56332)

YCrCb to RGB Color-Space Converter (7.1)

Version 7.1
Added auto upgrade support from previous version.
The GUI (Features - Converter Type - Input Range Selection) has been changed to Output Range Selection
Reduced warnings in synthesis and simulation
Added support for out of context flow
Updated constraints to match IP hierarchy
Added support for Cadence IES and Synopsys VCS simulators
Removed C model dependency on stlport (STL Portability) library; C model now uses STL built into the compiler
Windows C model DLLs are statically linked to the Windows C run-time (CRT) library, to remove the runtime dependency on MSVCRT90.dll, which can cause problems when using the C model in a Windows compiler other than Visual Studio 2008

ZYNQ7 Processing System (5.3)

Version 5.3
Added Microzed board preset In ps7 ip
xz0303 SBG package added
TCL based preset support for Zynq
Zynq BFM subcore added for simulation support

ZYNQ7 Processing System BFM (2.0)

Version 2.0
Removed all AXI_RESET output signals.
Moved all the port names to lower case.
Added support for all 16 IRQ_F2P pins.

interrupt_controller (3.0)

Version 3.0
No changes

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AR# 58605
日期	06/24/2014
状态	Archive
Type	版本说明
Tools	Vivado Design Suite - 2013.3

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AR# 58605

2013.3 Vivado IP Release Notes - All IP Change Log Information

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