This answer record helps you find all Zynq UltraScale+ MPSoC solutions related to boot and configuration known issues.
Note: This answer record is part of Xilinx Zynq UltraScale+ MPSoC Solution Center (Xilinx Answer 64375).
The Xilinx Zynq UltraScale+ MPSoC Solution Center is available to address all questions related to Zynq UltraScale+ MPSoC.
Whether you are starting a new design or troubleshooting a problem, use the Zynq UltraScale+ MPSoC Solution Center to guide you to the right information.
Find all you need to know about booting a Zynq UltraScale+ MPSoC device (including Boot Time Estimates).
| (Xilinx Answer 65468) | Zynq UltraScale+ MPSoC - Booting a Zynq UltraScale+ MPSoC Device |
Top Xilinx Answer Records on Boot and Configuration
| (Xilinx Answer 65463) | Zynq UltraScale+ MPSoC - What devices are supported for configuration? |
| (Xilinx Answer 66740) | Zynq UltraScale+ MPSoC - What are the PL configuration bitstream lengths for the Zynq UltraScale+ MPSoC devices? |
Top Xilinx Answer Records on Debugging Programming/Booting
| (Xilinx Answer 68656) | Zynq UltraScale+ MPSoC: QSPI Programming/Booting Checklist |
| (Xilinx Answer 66436) | XSDB is not able to connect to PSU after successfully booting in SD mode on a ZCU102 board |
| (Xilinx Answer 66437) | psu_post_config (from psu_init.tcl) sometimes hangs on a ZCU102 board |
Known issues for VIVADO/XSDK programming flash tools
| Xilinx Answer | Title | Tool Version Found | Tool Version Resolved |
| (Xilinx Answer 70310) | 2017.3 Zynq UltraScale+ MPSoC: XSDB and Vivado HW Manager fail QSPI programming on a DDR-less board | 2017.3 | 2018.1 |
| (Xilinx Answer 69928) | 2017.3 Zynq UltraScale+ MPSoC: Low Performance during Flash (QSPI and NAND) Programming | 2017.3 | 2017.4 |
| (Xilinx Answer 69629) | 2017.1/2017.2 SDK- Zynq UltraScale+ MPSOC, Program Flash failed using FSBL with DDR ECC enabled | 2017.1 | 2017.3 |
| (Xilinx Answer 69168) | 2016.x/2017.1 Zynq UltraScale+ MPSoC - QSPI programming fails for Dual Stacked Configuration | 2016.1 | 2017.3 |
| (Xilinx Answer 68237) | 2016.x/2017.1 Zynq UltraScale+ MPSoC - QSPI programming requires the QSPI Feedback Clock on MIO6 | 2016.1 | 2017.3 |
| (Xilinx Answer 66715) | QSPI programming on an ZCU102 board requires the Zynq UltraScale+ device to boot in JTAG mode | 2016.1 | 2017.3 |
Known Configuration related issues for u-boot
| Xilinx Answer | Title | Tool Version Found | Tool Version Resolved |
| (Xilinx Answer 69992) | 2017.3 Zynq UltraScale+ MPSoC: Removed Authentication support in u-boot for bitstream and images loading | 2017.3 | 2018.1 |
| (Xilinx Answer 69381) | 2017.2 Zynq UltraScale+ MPSoC: U-boot 'sf test' command failed for QSPI x4 at 100Mhz | 2017.2 | 2017.3 |
| (Xilinx Answer 69757) | 2017.1/2 Zynq UltraScale+ MPSoC: PetaLinux fails to compile u-boot with link error after UBI command line is enabled. | 2017.1 | 2017.3 |
| (Xilinx Answer 69240) | Zynq UltraScale+ MPSoC Example Design: How to program and boot from QSPI x1 (MOSI-MISO)? | 2017.1 | N.A. |
| (Xilinx Answer 69382) | 2017.1/2017.2 Zynq UltraScale+ MPSoC: U-boot takes too long to copy the Linux images from QSPI to DDR | 2017.1 | T.B.D. |
| (Xilinx Answer 69332) | 2017.1 Zynq UltraScale+ MPSoC: U-boot needs a patch to run eMMC at HS200 | 2017.1 | 2017.3 |
| (Xilinx Answer 69383) | 2017.1/2 Zynq UltraScale+ MPSoC: U-Boot support to load encrypted bitstream | 2017.1 | N.A. |
| (Xilinx Answer 68831) | Zynq UltraScale+ MPSoC: 2016.4 u-boot fails to write ondie-ECC NAND | 2016.4 | 2017.3 |
| (Xilinx Answer 68476) | Zynq UltraScale+ MPSoC - 2016.3 u-boot - cannot probe Spansion QSPI flash in dual parallel mode | 2016.3 | 2017.1 |
| (Xilinx Answer 68061) | 2016.3 Zynq UltraScale+ MPSoC, Create Boot Image: u-boot image fails to boot | 2016.3 | N.A. |
| (Xilinx Answer 68657) | Zynq UltraScale+ MPSoC: How to use u-boot to program a "known to work" QSPI flash? | N.A. | N.A. |
| (Xilinx Answer 66438) | On ZCU102 QSPI24 warm booting hangs if u-boot was previously executed | N.A. | N.A. |
Known issues for XSDK FSBL
| Xilinx Answer | Title | Tool Version Found | Tool Version Resolved |
| (Xilinx Answer 70622) | Zynq UltraScale+ MPSoC: 2017.x Xilinx Development tools and software re-use the same AES Key and IV pair across multiple partitions. | 2017.x | 2018.1 |
| (Xilinx Answer 70302) | 2017.4 Zynq UltraScale+ MPSoC: FSBL error of XFSBL_DECRYPT:XFSBL_ERROR_BITSTREAM_GCM_TAG_MISMATCH | 2017.4 | 2018.1 |
| (Xilinx Answer 70005) | 2017.2/3 Zynq UltraScale+ MPSoC: FSBL Boot image with Key Rolling causes XFSBL Tag Mismatch error | 2017.2 | 2018.1 |
| (Xilinx Answer 70133) | Zynq UltraScale+ MPSoC: Secure Boot fails without FSBL prints on the UART | N.A. | N.A. |
| (Xilinx Answer 70232) | 2017.3 Zynq UltraScale+ MPSoC Processing System IP: "Generate Output Products" is not running when only Isolation Configuration parameters are changed | 2017.3 | 2017.4 |
| (Xilinx Answer 69960) | Zynq UltraScale+ MPSoC, Zynq-7000, Vivado 2017.3 - Upgrading to 2017.3 without validating can corrupt the Processing System Block | 2017.3 | 2017.4 |
| (Xilinx Answer 70228) | Zynq UltraScale+ MPSoC, Vivado 2017.3 - PS DDR Does not work correctly in hardware, but did work in Vivado 2017.2 and earlier | 2017.3 | 2017.4 |
| (Xilinx Answer 69688) | 2017.2 Zynq UltraScale+ MPSoC: FSBL SD boot failed with data abort exception when a53_64 targeted application is running at upper PS DDR or PL DDR memory | 2017.2 | 2017.3 |
| (Xilinx Answer 70237) | 2017.1 - 2017.3 Zynq UltraScale+ MPSoC FSBL: Isolation Configuration is bypassed (except for OCM) | 2017.1 | 2017.4 |
| (Xilinx Answer 69240) | Zynq UltraScale+ MPSoC Example Design: How to program and boot from QSPI x1 (MOSI-MISO)? | 2017.1 | N.A. |
| (Xilinx Answer 69153) | Zynq UltraScale+ MPSoC, JTAG Boot fails if PMUFW is loaded and run after FSBL | 2017.1 | N.A. |
| (Xilinx Answer 69269) | Zynq UltraScale+ MPSoC, SDK - Debugging FSBL application does not show source code | 2017.1 | N.A. |
| (Xilinx Answer 69108) | 2017.1 Zynq UltraScale+ MPSoC: xilpm library fails to build | 2017.1 | 2017.3 |
| (Xilinx Answer 68732) | 2017.1 Zynq UltraScale+ MPSoC, Boot Image fails to boot if bitstream is placed after ATF | 2017.1 | N.A. |
| (Xilinx Answer 68956) | Zynq UltraScale+ MPSoC, 2016.4 SDK Unable to debug Aarch32 FSBL for A53 | 2016.4 | 2017.1 |
| (Xilinx Answer 69149) | 2016.4 Zynq UltraScale+ MPSoC: FSBL fails to decrypt bitstream if the image is place in QSPI at a multiple of 32K offset | 2106.4 | 2017.1 |
| (Xilinx Answer 68582) | Zynq UltraScale+ MPSoC: 2016.4 FSBL hang when DDR ECC is enabled | 2016.4 | 2017.1 |
| (Xilinx Answer 68210) | Design Advisory for Zynq UltraScale+ MPSoC: FSBL authenticates the boot image in external DDR | 2016.3 | 2017.1 |
| (Xilinx Answer 68969) | Zynq UltraScale+ MPSoC: 2016.x FSBL fails to load an R5 application with SHA3 checksum | 2016.3 | 2017.1 |
| (Xilinx Answer 67953) | Zynq UltraScale+ MPSoC, 2016.3 FSBL and PMUFW: Support for Isolation (Enhanced Security Configuration) | 2016.3 | N.A. |
| (Xilinx Answer 67955) | Zynq UltraScale+ MPSoC, 2016.3 FSBL: Adding XFsbl_HookPsuInit() allows you to load alternative psu_init | 2016.3 | N.A. |
| (Xilinx Answer 68166) | Zynq UltraScale+ MPSoC - PS-PL AXI widths not configured in 2016.3 FSBL | 2016.3 | 2016.4 |
| (Xilinx Answer 68005) | Zynq UltraScale+ MPSoC: 2016.3 FSBL fails to load latest PMUFW in NAND boot mode. | 2016.3 | 2017.1 |
| (Xilinx Answer 68001) | Zynq UltraScale+ MPSoC, 2016.3 FSBL: Vectors region overwritten in R5 with secure partitions. | 2016.3 | 2017.1 |
| (Xilinx Answer 67954) | Zynq UltraScale+ MPSoC, 2016.3 FSBL: Memory Layout changes | 2016.3 | N.A. |
| (Xilinx Answer 68211) | Zynq UltraScale+ MPSoC - FSBL does not initialize above first 2GB of PS DDR when using ECC, causing program exceptions | 2016.3 | 2016.4 |
| (Xilinx Answer 67987) | Zynq UltraScale+ MPSoC: 2016.3 FSBL and psu_init.tcl TCM ECC Initialization | 2016.3 | 2017.1 |
| (Xilinx Answer 67569) | Zynq UltraScale+ MPSoC - 2016.2 FSBL Configuration Performs Degrades When XFSBL_PERF Mode Is Enabled | 2016.2 | 2016.3 |
| (Xilinx Answer 66295) | Zynq UltraScale+ MPSoC Processing System IP - PS-PL AXI Interfaces do not function correctly at 64-bit or 32-bit widths (or 128-bits for M_AXI_HP0_LPD) | 2016.1 | 2017.1 |
| (Xilinx Answer 67414) | Zynq UltraScale+ MPSoC: 2016.2/2016.1 FSBL unable to load PMU_FW in SD and eMMC boot mode on ZCU102 board | 2016.1 | 2016.3 |
| (Xilinx Answer 65971) | FSBL EL3 stack size is unused | 2015.4 | 2016.1 |
| (Xilinx Answer 66523) | Zynq UltraScale+ MPSoC: FSBL for ZCU102 requires I2C interface | 2015.4 | TBD |
Known issues for XSDK Bootgen
| Xilinx Answer | Title | Tool Version Found | Tool Version Resolved |
| (Xilinx Answer 69241) | 2017.1 bootgen has an issue where xip_mode generates the proper ARM Vector Table in the image ONLY for R5 and A53-32bit. | 2017.1 | 2017.2 |
| (Xilinx Answer 68699) | SDK 2016.4 - Zynq UltraScale+ MPSoC: BootGen does not support 64-bit load addresses in .elf files | 2016.4 | 2017.2 |
| (Xilinx Answer 68396) | 2016.3/2016.4 SDK - Secure Boot Image fails to boot on Zynq UltraScale+ ES2 Silicon | 2106.3 | 2017.1 |
| (Xilinx Answer 68170) | SDK 2016.3- Zynq UltraScale+ MPSoC: BootGen does not support ZU19 parts | 2016.3 | 2016.4 |
| (Xilinx Answer 66861) | Creating a boot image, the destination of the bitstream should be PL instead of A53 | 2016.1 | 2016.2 |
| (Xilinx Answer 65969) | Create Boot Image does not support Zynq UltraScale+ MPSoC | 2015.4 | 2016.1 |
| (Xilinx Answer 66383) | Zynq UltraScale+ MPSoC - Are Example BIF Files Available for BootGen? | 2015.4 | N.A. |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 64375 | Xilinx Zynq UltraScale+ MPSoC Solution Center | N/A | N/A |
| 66183 | Zynq UltraScale+ MPSoC 处理系统 IP - 发布说明和已知问题 | N/A | N/A |
| Answer Number | 问答标题 | 问题版本 | 已解决问题的版本 |
|---|---|---|---|
| 65971 | 2015.4 - Zynq UltraScale+ MPSoC: FSBL EL3 stack size is unused | N/A | N/A |
| AR# 65467 | |
|---|---|
| 日期 | 04/09/2018 |
| 状态 | Active |
| Type | 解决方案中心 |
| 器件 | |