This master answer record for the Virtex-5 Endpoint Block Plus Wrapper for PCI Express core lists all release notes, Design Advisories, Known Issues and general information answer records for different versions of the core.
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This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) - Xilinx Solution Center for PCI Express
Release Notes:
| (Xilinx Answer 23985) | Release Notes v1.1 |
| (Xilinx Answer 24603) | Release Notes v1.2 |
| (Xilinx Answer 25162) | Release Notes v1.3 |
| (Xilinx Answer 25493) | Release Notes v1.4 |
| (Xilinx Answer 29468) | Release Notes v1.5 |
| (Xilinx Answer 30120) | Release Notes v1.6 |
| (Xilinx Answer 30632) | Release Notes v1.7 |
| (Xilinx Answer 30980) | Release Notes v1.8 |
| (Xilinx Answer 31572) | Release Notes v1.9 |
| (Xilinx Answer 32274) | Release Notes v1.10 |
| (Xilinx Answer 32741) | Release Notes v1.11 |
| (Xilinx Answer 33278) | Release Notes v1.12 |
| (Xilinx Answer 33762) | Release Notes v1.13 |
| (Xilinx Answer 35321) | Release Notes v1.14 |
| (Xilinx Answer 42760) | Release Notes v1.15 |
Design Advisories:
| (Xilinx Answer 33580) | Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express Master Answer Record |
| (Xilinx Answer 34444) | Design Advisory for the Endpoint Block Plus Wrapper v1.13 for PCI Express - Transmit Stall Due to Link Partner Advertisement of Data Limited Completion Credits |
| (Xilinx Answer 33699) | Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Polarity Reversal on Lane 7 Could Cause the Core Not to Train all 8 Lanes |
| (Xilinx Answer 33534) | Design Advisory for the Endpoint Block Plus for PCI Express Wrapper v1.12 for PCI Express - Using Synplify with the Block Plus Wrapper Source Code Delivery |
| (Xilinx Answer 33411) | Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - After warm reset, TX direction stalls forever because of deassertion of trn_tdst_rdy_n |
| (Xilinx Answer 33709) | Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Improve Timing Closure |
| (Xilinx Answer 33710) | Design Advisory for the Endpoint Block Plus Wrapper v1.12 for PCI Express - Extended deassertions of trn_rnp_ok_n could result in completions being blocked inside the core |
Known Issues/General Information:
| (Xilinx Answer 30124) | Endpoint Block Plus Wrapper for PCI Express - Patch updates for Endpoint Block Plus Wrapper for PCI Express |
| (Xilinx Answer 31164) | Endpoint Block Plus Wrapper v1.8 for PCI Express - MPS of 128 or 256 bytes causes received TLP bit errors due to Expansion ROM work-around |
| (Xilinx Answer 31460) | Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - The default TXPREEMPHASIS value is incorrect for FXT devices on page 7 of the CORE Generator Customization GUI |
| (Xilinx Answer 32091) | Endpoint Block Plus Wrapper v1.11 for PCI Express - Downstream Port model drops completions with length 64 bytes and greater |
| (Xilinx Answer 32727) | Endpoint Block Plus Wrapper v1.11 for PCI Express - MAP fails to complete due to predictable IP placement constraints |
| (Xilinx Answer 32946) | Endpoint Block Plus Wrapper v1.11 for PCI Express - Syntax error in x1 board_dual.v causes simulation failures |
| (Xilinx Answer 33850) | Endpoint Block Plus Wrapper v1.13 for PCI Express - Reading and Writing Configuration Space Registers Fails |
| (Xilinx Answer 34706) | Endpoint Block Plus Wrapper v1.15 for PCI Express - Disconnecting Packets on TX Interface when Interfacing with a link Partner Advertising Non-Infinite Completion Credits Can Eventually Stall the Transmit Interface |
| (Xilinx Answer 37246) | Endpoint Block Plus Wrapper v1.14 for PCI Express - Possible inbound packet loss if a 8b10b error occurs while previous packet is being written into receive block RAM |
| (Xilinx Answer 31210) | Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Interrupt Status bit not set when generating Legacy Interrupt |
| (Xilinx Answer 31211) | Endpoint Block Plus Wrapper v1.12 for PCI Express - Link transitioning to L0s causes BAR settings to be reset |
| (Xilinx Answer 31646) | Endpoint Block Plus Wrapper v1.14 for PCI Express - Dual core UCF problems |
| (Xilinx Answer 31647) | Endpoint Block Plus Wrapper v1.12 for PCI Express - Dual core implement_dual.bat file missing |
| (Xilinx Answer 31843) | Endpoint Block Plus Wrapper v1.9 for PCI Express - Power management transition from D0 to D3hot to D0 can cause transmit stall |
| (Xilinx Answer 31850) | Endpoint Block Plus Wrapper v1.12 for PCI Express - Simulation testbench writes to incorrect address for Device Control Register |
| (Xilinx Answer 33400) | Endpoint Block Plus Wrapper v1.12 for PCI Express - ModelSim simulation results in numerous signals trimmed from the wave dump |
| (Xilinx Answer 33401) | Endpoint Block Plus Wrapper v1.12 for PCI Express - "ERROR:sim:159 - An internal error has occurred - when disabling TX_DIFF_BOOST |
| (Xilinx Answer 33410) | Endpoint Block Plus Wrapper v1.12 for PCI Express - Compatibility issues with ISE Project Navigator because of PIO_EP.v file module declarations and 64-bit interface ifdef declaration |
| (Xilinx Answer 33421) | Endpoint Block Plus Wrapper v1.11 for PCI Express - Core generated for x2 lanes, Virtex-5 FXT or TXT, will not link up |
| (Xilinx Answer 33937) | Endpoint Block Plus Wrapper for PCI Express - The implement.sh[bat] file errors out during synthesis of the wrapper files |
| (Xilinx Answer 33939) | Endpoint Block Plus Wrapper v1.12 and later for PCI Express - How to create an NGC file of the Block Plus Wrapper files |
| (Xilinx Answer 51600) | Endpoint Block Plus Wrapper v1.15 for PCI Express - Example Design Simulation Fails for x8 Configuration Article |
| (Xilinx Answer 42368) | Virtex-5 Integrated PCI Express Block Plus - Debugging Guide for Link Training Issues |
| (Xilinx Answer 46888) | Virtex-5 Endpoint Block Plus for PCI Express - Debugging and Packet Analysis Guide with Downstream Port Model and PIO Example Design |
| (Xilinx Answer 47109) | Virtex-5 Endpoint Block Plus for PCI Express - Value for cfg_interrupt_mmenable signal Article |
| (Xilinx Answer 30107) | Endpoint Block Plus Wrapper for PCI Express - What output should be expected when running the PIO example simulation? |
| (Xilinx Answer 31376) | Endpoint Block Plus Wrapper v1.8 for PCI Express - Transmit Lockup on First Completion Transmitted after Link Up |
| (Xilinx Answer 31419) | LogiCORE Endpoint Block Plus for PCI Express - ML555 not recognized by system. What is the pinout for the ML555 board? |
| (Xilinx Answer 31704) | Endpoint Block Plus Wrapper v1.10 and v1.10.1 for PCI Express - Importing a v1.8 XCO to v1.9 causes "Error:sim228 -An Invalid core configuration has been detected during Customization. |
| (Xilinx Answer 34183) | Endpoint Block Plus Wrapper v1.13 for PCI Express - How to generate an NGC from the source files |
| (Xilinx Answer 29236) | Endpoint Block Plus Wrapper for PCI Express - How should the user application respond to requests targeting Expansion ROM? System hangs during Boot process |
| (Xilinx Answer 31284) | Endpoint Block Plus Wrapper v1.9 for PCI Express - Per Vector Masking Bit incorrectly set inside MSI Control Register |
| (Xilinx Answer 32270) | Endpoint Block Plus Wrapper v1.9 for PCI Express - Using non-synchronous links with Virtex-5 FXT (GTX RocketIO) could result in data errors |
| (Xilinx Answer 33643) | Endpoint Block Plus Wrapper v1.12 for PCI Express - Cannot implement the core in Project Navigator |
| (Xilinx Answer 36783) | Endpoint Block Plus Wrapper v1.14 for PCI Express - Finite completion attribute not set correctly |
| AR# 51597 | |
|---|---|
| 日期 | 01/28/2016 |
| 状态 | Active |
| Type | 综合文章 |
| IP | |