The following answer records cover current known issues as well as commonly asked questions related to configuration.
Note: This answer record is part of the Xilinx Configuration Solution Center (Xilinx Answer 34904)
The Xilinx Configuration Solution Center is available to address all questions related to Configuration.
UltraScale and UltraScale+
| (Xilinx Answer 66570) | UltraScale Architecture Soft Error Mitigation Controller - Guidance for testing with error injection |
| (Xilinx Answer 63609) | UltraScale and UltraScale+ Soft Error Mitigation Controller - Release Notes |
| (Xilinx Answer 63857) | UltraScale External DONE pull-up recommendation |
7 Series
| (Xilinx Answer 57045) | Design Advisory for Artix-7, Kintex-7 - When CFGBVS is set to VCCO of Bank 0, then Banks 14 and 15 are limited to 3.3V or 2.5V for Configuration |
| (Xilinx Answer 44942) | Virtex-7, Kintex-7, Artix-7 FPGA Configuration - BUSY Pin Removal |
| (Xilinx Answer 42543) | 7 Series Configuration - Fallback is disabled by default; Multiboot image does not fallback |
| (Xilinx Answer 43174) | 7 Series - PROGRAM_B pin held Low prior to power-up does not delay configuration |
| (Xilinx Answer 42544) | 7 Series Configuration - When Fallback is enabled, the device status register is always cleared after a failed configuration attempt |
| (Xilinx Answer 41782) | 7 Series - Why is there no longer a recommendation for Thevenin termination on the CCLK pin for configuration? |
| (Xilinx Answer 41298) | SelectIO 7 Series - What power rail supplies the dedicated configuration pins? (MODE pins, JTAG pins etc.) |
| (Xilinx Answer 47449) | Virtex-7 XC7VX690T Initial Engineering Sample (IES) - iMPACT Verify fails and Configuration Readback does not work correctly unless PCIe DRP is instantiated |
| (Xilinx Answer 50489) | 7 Series - ERROR:Bitgen:145 - Why are RS0 and RS1 pins persisted if the design is not using Multiboot and the BitGen ConfigFallback option is not set? |
| (Xilinx Answer 51337) | 7 Series - How can I work around the Fallback limitation for 32-bit addressing in SPI mode? |
| (Xilinx Answer 51473) | 7 Series - Which dual mode configuration pins do the "BitGen -g persist:yes" option apply to on 7 Series devices? |
| (Xilinx Answer 52626) | 7-Series - STARTUPE2_USRCCLK0 ignores first two clock cycles at output |
| (Xilinx Answer 53903) | 7 Series - When the Readback CRC and AES bistream encryption features are both enabled, the Readback CRC requires the ICAP to be included in the design to function |
| (Xilinx Answer 44635) | 7 Series - EMCCLK considerations to ensure the FPGA completes the startup sequence |
Older Architecture
| (Xilinx Answer 32653) | Spartan-3/-3E/-3A/-3AN/-3DSP Families - I/O's glitch during power up or down, or a PROG_B pulse |
| (Xilinx Answer 33575) | Spartan-6 FPGA - JTAG Configuration Setup For Designs Using GTPs |
Vivado Hardware Manager
| (Xilinx Answer 69758) | Vivado: How do I get a standalone version of Vivado Programming Tools to run in the lab? |
| (Xilinx Answer 66440) | Vivado - Linux OS - Digilent and Xilinx USB cable installation check |
| (Xilinx Answer 59128) | Is it possible to (re)install the Xilinx USB/Digilent cable drivers without a full reinstall of Vivado Design Suite? |
| (Xilinx Answer 52881) | Configuration - BitStream Encryption - How to create and program an encrypted bitstream |
| (Xilinx Answer 54939) | 2013.x Vivado, 14.5/6 iMPACT, Flash Programming, ChipScope, PromGen - I do not see iMPACT or ChipScope when I install the Vivado 2013.1 tools |
| (Xilinx Answer 61312) | Non IEEE 1149.3 compliant devices are not recognized in the JTAG chain |
| (Xilinx Answer 66954) | Intermittent configuration failures can occur when the FPGA is power cycled and the programming cable is connected |
| (Xilinx Answer 65328) | 2015.3 Vivado Device Programmer - UltraScale - Direct configuration of RSA Authenticated bitstreams not supported |
| (Xilinx Answer 55660) | Vivado Constraints - How to resolve DRC Warning:[DRC 23-20] Rule violation (CFGBVS-1) Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design |
| (Xilinx Answer 58406) | 2013.2 Hardware Manager - ERROR:[Labtools 27-1974] Mismatch between the design programmed into the device XC7K325T_0 and the probes file |
iMPACT
| (Xilinx Answer 47890) | 14.x iMPACT - Known Issues for the iMPACT 14.x tools |
| (Xilinx Answer 476) | PROMGen - Description of PROM/EEPROM file formats: MCS, EXO, HEX, and others |
| (Xilinx Answer 52881) | Configuration - BitStream Encryption - How to create and program an encrypted bitstream |
| (Xilinx Answer 23174) | PROMGen - Is it possible to convert an MCS file into a BIN (HEX or EXO) file? |
| (Xilinx Answer 16996) | Vivado/ISE - How does the bitstream compress option work (MFWR - Multiple Frame Write Register)? How much compression will be achieved? |
| (Xilinx Answer 14468) | BitGen - Explanation of output files (.bit, .rbt, .bgn, .drc, msk, .ll, .nky, .rba, .rbb, .rbd, .msd, .bin) |
| (Xilinx Answer 36210) | PROMGen - How can file formats be changed or have files bitswapped? |
| (Xilinx Answer 34599) | iMPACT - Status Register read shows all '0' |
| (Xilinx Answer 8902) | iMPACT - What is "IDCODE looping?" |
| (Xilinx Answer 11857) | iMPACT - What is "Initialize Chain"? |
| (Xilinx Answer 24024) | iMPACT - How can the data from the Status Register be used to debug configuration issues? |
| (Xilinx Answer 34909) | iMPACT - What do the different bits in a Status Register Read and BOOTSTS mean? |
| (Xilinx Answer 13529) | iMPACT - "ERROR: iMPACT:583) - '2' The IDCODE read from the device does not match the IDCODE in the BSDL file" |
| (Xilinx Answer 44237) | 13.3 - BitGen - 7 Series - DonePipe option is now enabled by default |
Cables
| (Xilinx Answer 54381) | Xilinx Programming Cables - Platform Cable USB and Parallel Cable IV - Driver install FAQ |
| (Xilinx Answer 54382) | Digilent Programming Cables - Driver Install FAQ |
| (Xilinx Answer 66440) | Vivado - Linux OS - Digilent and Xilinx USB cable installation check |
| (Xilinx Answer 59128) | Is it possible to (re)install the Xilinx USB/Digilent cable drivers without a full reinstall of Vivado Design Suite? |
| (Xilinx Answer 35924) | 10.1, 11.x - ISE - Installation of Cable Drivers for ISE 10.1, 11.x on Windows 7 |
| (Xilinx Answer 20429) | Platform Cable USB - Frequently Asked Questions (FAQs) |
| (Xilinx Answer 44397) | 13.x/14.x iMPACT - Cable Driver Installation - Installation passes on Windows 7 but the Jungo driver Windrvr6 does not operate or appear in the device manager |
| (Xilinx Answer 64361) | Configuration - Cable Driver - The driver of JTAG USB cable cannot be installed in Ubuntu. |
| (Xilinx Answer 54382) | Digilent Programming Cables - Driver Install FAQ |
| (Xilinx Answer 30184) | iMPACT - "WARNING:iMPACT:923) - Cannot find cable, check cable setup" / "Cable connection failed" |
Generic Configuration Solution
| (Xilinx Answer 11433) | JTAG - Do the JTAG pins need external pull-ups? What should I do with unused JTAG pins? |
| (Xilinx Answer 3203) | JTAG - General description of the TAP Controller states |
| (Xilinx Answer 16832) | JTAG - What is a JTAG scan bridge, scan path linker, or JTAG multiplexer/JTAG mux? |
| (Xilinx Answer 42128) | FPGA Configuration - How many clock cycles should I apply to CCLK after DONE has gone High? |
| (Xilinx Answer 50163) | Tandem PROM - What signals are added to my design by using the Tandem PROM solution? |
| (Xilinx Answer 40212) | Configuration FPGA Multiboot - Can I multiboot a master and slave device at the same time in a parallel or slave daisy chain? |
| AR# 34104 | |
|---|---|
| 日期 | 01/10/2018 |
| 状态 | Active |
| Type | 解决方案中心 |
| 器件 | |