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Zynq-7000 SoC Design Hub - Design Overview

Design Resources

Design Resources

Hardware Development PlatformsDesign FilesDate
 DH0039 - ZC702 Evaluation Kit Design Hub 06/16/2021
 DH0040 - ZC706 Evaluation Kit Design Hub 06/16/2021
Application ResourcesDesign FilesDate
 DH0051 - Data Movers Design Hub 06/16/2021
 DH0052 - Power Management Design Hub 06/16/2021
 DH0053 - Boot, Config, and Security Design Hub 06/16/2021
 DH0054 - Performance & Acceleration Design Hub 06/16/2021
Application NotesDesign FilesDate
 XAPP1309 - Measured Boot of Zynq-7000 SoCsDesign Files03/07/2017
 XAPP1285 - Scaling LiveVideo with the Video Processing SubsystemDesign Files06/10/2016
 XAPP1266 - Using Quality of Service (QoS) Capabilities in Zynq-7000 SoC DevicesDesign Files09/18/2015
 XAPP1264 - Real Time Video Engine 3.1 Implementation in Zynq-7000 SoCs 12/03/2015
 XAPP1258 - Using VxWorks 7 BSP with the Zynq-7000 SoC 05/08/2015
 XAPP1256 - Isolation Design Flow Lab for Zynq-7000 SoCs (Vivado Tools)Design Files03/21/2016
 XAPP1251 - Xilinx Virtual Cable Running on Zynq-7000 Using the PetaLinux ToolsDesign Files04/30/2015
 XAPP1250 - Simulating High Performance Video Systems with Bus Functional ModelsDesign Files05/15/2015
 XAPP1249 - Implementing SMPTE SDI Interfaces with 7 Series GTX TransceiversDesign Files04/01/2018
 XAPP1243 - 1G to 10G Ethernet Dynamic Switching Using Xilinx High Speed Serial IO SolutionDesign Files10/06/2017
 XAPP1231 - Partial Reconfiguration of a Hardware Accelerator with Vivado Design SuiteDesign Files03/19/2015
 XAPP1226 - Protecting Sensitive Information in Zynq-7000 SoCDesign Files11/19/2014
 XAPP1225 - Run Time Integrity and Authentication Check of Zynq-7000 SoC System MemoryDesign Files10/24/2014
 XAPP1224 - Updating a System Securely in the Zynq-7000 SoCDesign Files02/12/2015
 XAPP1223 - Changing the Cryptographic Key in Zynq-7000 SoCDesign Files02/20/2015
 XAPP1222 - Isolation Design Flow for Xilinx 7 Series FPGAs or Zynq-7000 SoCsDesign Files12/17/2020
 XAPP1221 - Using ENEA OSE BSP for the Zynq-7000 SoCDesign Files01/12/2015
 XAPP1219 - System Performance Analysis of an SoCDesign Files11/05/2015
 XAPP1216 - AXI Chip2Chip Reference Design for Real-Time Video ApplicationsDesign Files08/12/2014
 XAPP1206 - Boost Software Performance on Zynq-7000 SoC with NEONDesign Files06/12/2014
 XAPP1205 - Designing High-Performance Video Systems with the Zynq-7000 SoC Using IP IntegratorDesign Files03/28/2014
 XAPP1203 - Implementation of Signal Processing IP on Zynq-7000 SoC to Post-Process XADC SamplesDesign Files04/22/2014
 XAPP1185 - Zynq-7000 Platform Software Development Using the Arm DS-5 ToolchainDesign Files05/06/2014
 XAPP1184 - PIPE Mode Simulation Using Integrated Endpoint PCI Express Block in Gen2 x8 ConfigurationDesign Files
Design Files		01/16/2019
 XAPP1183 - Implementing Analog Data Acquisition using the Zynq-7000 SoC Processing System with the XADC AXI InterfaceDesign Files11/18/2013
 XAPP1182 - System Monitoring using the Zynq-7000 Processing System with a Xilinx Analog-to-Digital Converter AXI InterfaceDesign Files11/18/2013
 XAPP1175 - Secure Boot of Zynq-7000 SoCDesign Files01/14/2020
 XAPP1172 - Using the Zynq-7000 Processing System (PS) to Xilinx Analog to Digital Converter (XADC) Dedicated InterfaceDesign Files03/18/2014
 XAPP1171 - PCI Express Endpoint-DMA Initiator Subsystem Application NoteDesign Files11/04/2013
 XAPP1170 - Zynq-7000 SoC Accelerator for Floating-Point Matrix Multiplication using Vivado High-Level Synthesis (HLS)Design Files01/21/2016
 XAPP1160 - AXI Chip2Chip Reference Design for Real-Time Video ApplicationDesign Files07/03/2014
 XAPP1159 - Partial Reconfiguration of a Hardware Accelerator on Zynq-7000 SoC DevicesDesign Files01/21/2013
 XAPP1158 - Using VxWorks BSP with Zynq-7000 SoC 09/27/2013
 XAPP1095 - Real Time Video Engine 2.1 Implementation in Xilinx Zynq-7000 SoCs 01/31/2014
 XAPP1093 - Simple AMP: Zynq SoC Cortex-A9 Bare-Metal System with MicroBlaze ProcessorDesign Files01/24/2014
 XAPP1086 - Isolation Design Flow for Xilinx 7 Series FPGAs or Zynq-7000 SoCs (ISE Tools)Design Files02/05/2015
 XAPP1082 - PS and PL Ethernet Performance and Jumbo Frame Support with PL Ethernet in the Zynq-7000 SoCDesign Files07/16/2018
 XAPP1079 - Simple AMP: Bare-Metal System Running on Both Cortex-A9 ProcessorsDesign Files01/24/2014
 XAPP1078 - Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC ProcessorsDesign Files02/14/2013
 XAPP1026 - LightWeight IP (lwIP) Application Examples v4.0Design Files11/21/2014
 XAPP891 - AXI USB 2.0 Device: Demonstrating the Performance for Bulk and Isochronous TransfersDesign Files 
 XAPP890 - Zynq-7000 SoC Sobel Filter Implementation Using the Vivado High-Level Synthesis (HLS) ToolDesign Files09/25/2012
 XAPP794 - 1080p60 Camera Image Processing Reference DesignDesign Files12/20/2013
 XAPP792 - Designing High-Performance Video Systems with the Zynq-7000 SoCDesign Files10/16/2012
 XAPP745 - Processor Control of Vivado High-Level Synthesis (HLS) Designs 09/04/2012
 XAPP744 - Hardware In The Loop (HIL) Simulation for the Zynq-7000 SoCDesign Files11/02/2012
 XAPP742 - AXI VDMA Reference DesignDesign Files02/26/2014
 XAPP589 - All Digital VCXO Replacement for Gigabit Transceiver Applications (7 Series/Zynq-7000) 04/29/2015
 XAPP552 - Parameterizable CORDIC-Based Floating-Point Library OperationsDesign Files06/01/2012
White Papers Design FilesDate
 WP469 - Using the MicroBlaze Processor to Accelerate Cost-Sensitive Embedded System Development 06/06/2016
 WP468 - Leveraging Asymmetric Authentication to Enhance Security-Critical Applications Using Zynq-7000 SoCs 10/20/2015
 WP467 - A FIPS 140-2 Primer for the Zynq-7000 SoC 12/09/2016
 WP465 - Meeting Embedded HMI Requirements Using Zynq-7000 High-Performance SoCs 11/20/2015
 WP461 - Xilinx Reduces Risk and Increases Efficiency for IEC61508 10/13/2020
 WP460 - Reducing System BOM Cost with Xilinxapos;s Low-End Portfolio 01/26/2018
 WP459 - Leveraging Data-Mover IPs for Data Movement in Zynq-7000 SoC Systems 01/13/2015
 WP453 - High Performance Machine Vision Systems using Xilinx 7 Series Technology 07/13/2014
 WP452 - Adaptive Beamforming for Radar: Floating-Point QRD+WBS in an FPGA 06/24/2014
 WP445 - Enabling High-Speed Radio Designs with Xilinx FPGAs and SoCs 01/20/2014
 WP442 - Efficient Implementation of Analog Signal Processing Functions in Xilinx Devices 03/16/2018
 WP433 - Understanding and Mitigating System-Level ESD and EOS Events in Xilinx 7 Series Devices 06/24/2013
 WP429 - TrustZone Technology Support in Zynq-7000 SoC 05/20/2014
 WP426 - Secure Boot in the Zynq-7000 SoC 04/05/2013
 WP412 - The Xilinx Isolation Design Flow for Fault-Tolerant Systems 10/16/2013
 WP404 - Flexible Waveform Processing with the Xilinx Zynq-7000 Extensible Processing Platform 09/29/2011
 WP400 - Addressing the Graphics Revolution for Automotive Instrumentation Design Using FPGAs 08/30/2011
 WP383 - Achieving High Performance DDR3 Data Rates 08/29/2013
 WP378 - Xilinx Devices in Portable Ultrasound Systems 05/13/2013
 WP370 - Reducing Switching Power with Intelligent Clock Gating 08/29/2013
 WP312 - Xilinx Next Generation 28 nm FPGA Technology Overview 07/23/2013
Example DesignsDesign FilesDate
 AR51779 - Zynq-7000 SoC - Example Designs and Tech Tips 06/21/2018

Silicon Docs

Silicon Docs

Zynq-7000 Data SheetsDate
 DS190 - Zynq-7000 SoC Overview07/02/2018
 DS188 - Zynq-7000 SoC Overview for Automotive Devices07/02/2018
 DS196 - Zynq-7000Q SoC Overview for Defense-Grade Devices07/03/2018
 XMP087 - Zynq-7000 SoC Product Selection Guide06/05/2019
 DS187 - Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020): DC and AC Switching Characteristics Data Sheet12/01/2020
 DS191 - Zynq-7000 SoC (Z-7030, Z-7045, and Z-7100): DC and AC Switching Characteristics Data Sheet07/02/2018
 DS897 - Zynq-7000 SoC Bus Functional Model v2.0 Data Sheet04/06/2016
 DS176 - Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions v4.1 Data Sheet04/04/2018
Zynq-7000 User GuidesDate
 UG933 - Zynq-7000 SoC PCB Design and Pin Planning Guide03/14/2019
 UG865 - Zynq-7000 SoC Packaging and Pinout Specification07/28/2021
 UG1019 - Programming Arm TrustZone Architecture on the Xilinx Zynq-7000 SoC User Guide05/06/2014
 UG480 - 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide07/23/2018
 UG1181 - Zynq-7000 SoC Architecture Porting Guide10/22/2015
7 Series User GuidesDate
 UG482 - 7 Series FPGAs GTP Transceivers User Guide12/19/2016
 UG476 - 7 Series FPGAs GTX/GTH Transceivers User Guide08/14/2018
 UG479 - 7 Series FPGAs DSP48E1 Slice User Guide03/27/2018
 UG474 - 7 Series FPGAs Configurable Logic Block User Guide09/27/2016
 UG473 - 7 Series FPGAs Memory Resources User Guide07/03/2019
 UG472 - 7 Series FPGAs Clocking Resources User Guide07/30/2018
 UG471 - 7 Series FPGAs SelectIO Resources User Guide05/08/2018

Zynq-7000 SoC 设计

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Vivado Design Suite

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嵌入式设计